1.      Introduction to ASIC - SoC Design

History of VLSI Design

1. Introduction to ASIC - SoC Design

1.1.   IP Core Types

1.1.1. Soft Cores (RTL format)

1.1.2. Firm Cores (netlist format)

1.1.3. Hard Cores (GDSII format)

1.2. SoC Design Issues

 2.      IC Design Methodologies

2.1 Full Custom IC Design

5.2.1  Register inference

5.2.2 Mux Inference

5.2.3. Priority Encoder Inference

5.2.10. Pads separate from core logic

5.2.13. Registered outputs

5.2.14. Incomplete sensitivity list

5.2.16. Use Constants

5.2.17. General Coding guidelines for ASIC synthesis

6.      ASIC Synthesisis

6.2.1. Register Transfer Level (RTL) Representation

6.2.2. Constraints

6.2.3. Target Library

7.2 Basics of Logic Library (.lib)

7.2.1. Library group Scaling Factors:

14.3.Timing Constraints
14.4. Environmental constraints

14.5. Other Synopsys Design Constraints

15.  Process of logic synthesis: reading verilog, elaboration, synthesize

15.1. Provide search path and target technology library

15.2. Read HDL

15.3. Analyze

15.4. Elaborate

15.5. Linking

15.6. Read Constraints

15.7. Compile or Synthesize Methodology and Optimizations

15.8. Synthesize optimiization

15.8.1. Architectural(RTL) Optimization (technology independent optimization)

15.8.2. Logic-Level Optimization (tech independent optimization)(Global Focus Mapping)

15.8.3. Gate-Level Optimization (Incremental Optimization (IOPT))

16.  Synthesis Strategies for Designs : top-down, bottom-up

16.1. Top-Down Synthesis

16.2. Bottom-Up Synthesis

17.  How to improve synthesis optimization results?

17.1. Creating Path Groups

17.2. Ungrouping Hierarchies on the Critical Path

17.3. Optimizing Across Hierarchical Boundaries

18.  Outputs from Synthesis


[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009
[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009


  1. Hello, I see here nice outlines about ASIC. Can you show me where can I get their detail contents, please.
    Thanks sir!

    1. you will get detail contents soon... as and when it will be avaialable corresponding link will be enabled in this outlined list...

  2. why we are unable to see the topics from 14. Constraints: Clock, Logical DRC, Area, Power to
    18. Outputs from Synthesis. is it need to update or what?

  3. I am updating whenever i get time...please revisit the blog regularly !


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