Clock logic guidelines

5.2.11. Clock logic guidelines

In case of multiple clocks in the design, make sure that clock generation and reset logics are written in one module for better handling in synthesis. If a clock is used in different modules of different heirarchy then keep clock names common across all the modules. This makes constraining that clock easier and also supports better handling of synthesis scripts.

 

Ø  Don’t use mixed clock edges

mixing of edge sensitive and level sensitive lists are not allowed. Below code is a wrong one.

always @(posedge clk or posedge rst)

 

Ø  Avoid clock buffers or any other logic

If any signal crosses multiple clock domains having different clock frequencies then those signals must be properly synchronised with synchronous logic. Synthesis tools can’t optimize any timing paths between asynchronous clock domains.

References

[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005

[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009

[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009