01 December 2011

Synopsys Acquires Magma Design Automation

Well...... Finally the predicted is happening ! EDA major Synopsys is acquiring Magma Design Automation.
Here is the press release: Synopsys to Acquire Magma Design Automation

27 November 2011

Verilog HDL: Data Types

Value Set:
                           ---> Four values  to model the functionality

                           ---> Eight strengths of real hardware

    Value level--------- Condition in hardware circuits

            0 ------------- > Logic zero, false condition
            1 ------------- > Logic one, true condition
            X ------------ > Unknown logic value
            Z ------------- > High impedance ,floating state

Verilog HDL: Expressions, Operators and Operands

Dataflow modeling in Verilog describes the design in terms of expressions, instead of primitive gates. ‘expressions,, ‘operators’ and ‘operands’ form the basis of Verilog dataflow modeling.

Arithmetic:

                            *       ---> Multiplication
                            /        ---> Division
                           +        ---> Addition
                           -         ---> Subtraction
                           %       ---> Modulo
                          **        ---> Power or exponent

26 November 2011

Verilog HDL: Operators, Number Specification, Underscore Characters, Strings, Identifiers and Keywords, Escaped Identifiers

Operators:

Unary          : Precede the operand; always comes left of the operand. Eg: a=~b;
Binary         : Appear between two operands. Eg: a=b&&c;
Conditional : Have two separate operators that separate three operands. Eg: a=b?c:d;

 

12 November 2011

Verilog HDL-Ports

Ports

  • Ports provide the interface by which a module can communicate with its environment. (This is how technically it is defined by famous authors !!)
  • Also referred to as terminals. (As per Verilog terminology)

Eg :

module fulladd4(sum,c_out,a,b,c_in); //module with a list of ports

module top;                                        //No list of ports, top level module in simulation


11 November 2011

Verilog HDL-Modules

Verilog is a one of the famous Hardware Descriptive Languages (HDL). (VHDL is the other one). Verilog langauage syntax very well matches with C language syntax. This is big advantage in learning Verilog. Logic operators, data types, loops are similar to C. In addition to this certain data types which are necessary to describe a hardware are available in Verilog. For example, nets in a schematic or hardware design is refered here as ‘wire’. Flip-flops (or in general are called as registers) are defined as type ‘reg’.


“module”s are building block of Verilog. Consider any design represented by a block diagram with its inputs and outputs.


10 January 2011

Fixing Transition Violation

Transition violations can be fixed by different methods based on the design situations.


 
They include:

 
  • Up sizing the driver cell 
  • Decreasing the net length by moving cells nearer or reducing long routed net 
  • By adding buffers 
  • By using existing spare cells as buffers 
  • By splitting loads through buffers to reduce the fan out number (number of driven cells)