12 September 2009

Setup Time and Hold Time-Story of Poor Flip-Flop !

It is always interesting to talk about setup and hold!! Don’t think that if anybody asks questions related to setup time and hold time, he or she doesn’t know about setup and hold. He or she may know everything about setup time and hold time, time being it confuses. The term “setup” and “hold” is such a word in this VLSI – ASIC design world which only creates continuous questions, hard to explain in words, at least i myself is concerned! I remember, during my MTech days my professor used to say always "whole VLSI world is depending on two pillars, setup time and hold time". It would be more realistic if i say that he used to scold us !!

29 August 2009

MULTIPLEXING 7 SEGMENT DISPLAY USING PIC MICROCONTROLLER

 Let us try to understand about multiplexing of seven segment display using PIC microcontroller to implement decimal counter which will increment 0000 to 9999.

Seven Segment Displays are arrays of seven “Light Emitting Diode” (LED) segments with additional decimal point (dp) which is also a LED. Each these segments are marked as a,b,c,d,e,f,g and dp.


Fig 1

09 June 2009

Free download: OpenSPARC 64 bit processor and Nangate 45nm Open Cell Library

OpenSPARC is free 64 bit processor provided by Sun Microsystems. They are available in two flavours:

  • A 64-bit, 32 Thread Chip Multithreaded Microprocessor
  • A 64-bit, 64 Thread Chip Multithreaded Microprocessor

These processors (RTL source files) can be downloaded from OpenSPARC website.

06 June 2009

Timing paths

Timing Path
Timing path is defined as the path between start point and end point where start point and end point is defined as follows:
Start Point:
All input ports or clock pins of a sequential element are considered as valid start point.
End Point:
All output port or D pin of sequential element is considered as End point.

31 May 2009

IMPLEMENTATION OF CHEBYSHEV TYPE –1(ORDER-2) BANDPASS FILTER

Filter Parameters:

Order, 2n = 2

Passband = 450Hz - 550Hz.

Sampling Frequency Fs = 2000Hz

Using “fdatool” of MATLAB software the obtained filter coefficient (truncated to 4th decimal point) are

b = [0.2374, 0, 0.2374]

a = [1, 0, 0.5]

These coefficients are scaled by a factor 4 and again truncated to give filter coefficients as,

b = [1, 0, 1 ]

a = [4, 0, 2 ]

Linear Difference equation representation: - From the filter coefficients we can write the transfer function as

H (z)= [1+0.Z-1-1.Z-2] / [4+0.Z-1+2.Z-2 ]

Converting above equation to linear difference equation form we have,

4y(n)+2(n-2) = x (n)-x (n-2)

y (n) = 1/4[x (n)-x (n-2)-2y(n-2)]

For n = 0, y (0) = 1/4[x (0)]…………………………….(1)

For n = 1, y (1) = 1/4[x (1)]…………………………….(2)

For n = 2, y (2) = 1/4[x (2)]-1/4[x (0)+2y(0)]…………..(3)

Hardware Implementation And Analysis:

All the hardware setup exercised in previous study of filter implementation remains the same. To implement this filter only software has to be changed.

All the discussion carried over the sampling frequency effect, noise rejection ability of the filter etc hold for this filter also. Thus the discussion and analysis of this filter is going to be a repetition of what we have said in earlier section instead let us look into the peculiar problem that we have faced in implementing this filter and how work around is sorted out to solve the problem.

Keenly observe the equation (3), we can observe that at one instance the value of 1/4[x (2)] becomes less than 1/4[x (0)+2y(0)] when this happens, the total result y (2) comes out to be a –ve value. How PIC can understand that it is a –ve data? It treats each data as a +ve binary number and accordingly processes it. Then how to come out of this mischievous loop?

There is one more problem, which is peeping out! The problem is after some looping of the software and assignment of present value to previous value .We may get y(0) values as –ve. At this junction, ¼[x (0)+(-2y(0)] may result a –ve output. Now we have to handle one more –ve number, which the PIC unaware of!

To get through all these obstacles we have set a flag bit to indicate the sign status of the each resultant output y0, y1 and y2 (of course, then as you know, it loops). If the number is –ve, the flag bit is set else it is cleared.

Now let us imagine that y (0) is –ve. Then 2y(0) will be a –ve number. Then instead of adding x (0) with 2y(0) (refer equation (3)), we should subtract 2y(0) from x(0). This result also may be a –ve number. To indicate sign condition of this temporary result one more flag bit ‘ tempflag’ is used. According to the sign condition of this ‘tempflag’, 1/4[x (0)+2y(0)] is either added with or subtracted from 1/4[x (2)]. In the case of subtraction once again the result may come out to be a –ve value. To eliminate this –ve value a fixed DC level is added to each output before it finally out ported to PIC ports. The fixed DC value is selected such a way that it is greater than or equal to the resultant maximum –ve value.

Initially to check the numbers are –ve or +ve numbers are simply subtracted and checked for borrow. If carry is borrowed number from which another number is subtracted is treated as a –ve number (by setting corresponding flag bit), else it is treated as +ve number (by clearing corresponding flag bits). When present output value is assigned to previous output value, corresponding flag condition is also assigned accordingly.

FLOWCHARTS:

MAIN PROGRAM:











SUBROUTINE ‘SUB1’:









SUROUTINE ‘SUB2’:







SUBROUTINE ‘ADD1’:







SUROUTINE ‘ADD2’:









SUBROUTINE ‘DELAY’:





References

1. “Digital Signal Processing” By Sanjit K.Mitra

2. “Digital Signal Processing” By P.Ramesh Babu

3. “Digital Filters” By T.J.Terrel and E.T.Powner

4. “BASIC Digital Signal Processing” By Gordon B. Lockart and Barry M.G.Cheetham

5. “Digital Signal Processing” By Alan V.Oppenheim and Ronald W.Schafer

6. “DSP Microprocessors: Advances and Automotive Applications” By Subra Ganeshan and Dr.Gopal Arvamudhan

7. PIC 16F87XA Data Sheet

8. Embedded Control Handbook-1994/95/Microchip

9. Microchip Technical Library CD-ROM-First Edition 2002

10. National Semiconductor CD-ROM-1995/96

11. “Design with PIC Microcontrollers” By John B.Peatman

12. “Opamps and Linear Integrated Circuits” By Ramakant A.Gayakwad

13. “Electronic Principles” By A.P.Malvino

www.mathworks.com

www.microchip.com

30 May 2009

IMPLEMENTATION OF II-ORDER CHEBYSHEV TYPE-I LOWPASS FILTER

Filter parameter: Fs=10KHz i.e. sampling time =1/10

=100us.

Fc = 2KHz

Apass = 1dB

Order n = 2

SOFTWARE SIMULATION: - The above filter is designed and simulated using “fdatool”, “simulink” and “dspfwiz” as explained in the earlier section.

HARDWARE IMPLEMENTATION: - To implement the filter in hardware we need to have a transfer function and its corresponding linear difference equation representation of the filter.

From the “fdatool” the obtained numerator and denominator coefficients are as follows,

Numerator b = 0.21797

0.43596

0.21798

Denominator a = 1.0000

-0.35135

0.32966

Since the PIC 16F877 Microcontroller does not directly support floating-point arithmetic, the numerator and denominator coefficients are equivalently converted to integer values by truncating and scaling by a factor of 4, which yields the filter coefficients as

b = [1, 2, 1]

a = [4, -1, 1].

Therefore,

Transfer function of the filter is,

H (z) = [ 1 + 2Z-1 + Z-2 ] / [4 - Z-1 + Z-2 ]

Converting the transfer function to linear difference equation we can write,

4y(n) – y (n-1) + y (n-2) = x (n) + 2x (n-1) + x (n-2)

Or y (n) = 1/4 [x (n) + 2x (n-1) + x (n-2) +y (n-1) – y (n-2)]

For n=0, y (0)=1/4[x (0)];

[Assuming the initial condition that x (-1), x (-2), y (-1) and y (-2) are zero].

For n=1, y (1)=1/4[x (1)+2x(0)-y (0)]

For n=2, y (2)=1/4[x (2)+2x(1)+x (0)+y (1)-y (0)]

Where x (0), x (1) and x (2) represents sampled values of input signal, y (0), y (1) and y(2) represents filtered output values.

FLOWCHART OF THE SOFTWARE: -















DELAY SUBROUTINE FLOWCHART:





HARDWARE SETUP: -The hardware setup for this filter implementation remains unchanged as shown in earlier blog post. Only change that we have is the design of RC lowpass filter.

Design:

Fc=Fs/2=5KHz; Let R=1.5KW.

Therefore,

C= 1/2*p*fc*R = 1/2*p*5K*1.5K=21.22nF

Therefore,

C selected=22nF

FREQUENCY RESPONSE: - The observed frequency response of the filter is as listed below,

Input voltage Vi=0.5v

Input Frequency (Hz) Output voltage (volts)

100----------5

200-----------5

400----------- 5

600----------- 5

800----------- 5

1K --------- --5

1.2K----------5

1.4K----------5

1.5K----------4.6

1.6K-----------4.5

1.8K---------- 4.0

1.9K-----------3.8

2.0K-----------3.5

2.1K-----------3.2

2.2K-----------3.0

2.4K-----------2.5

2.6K-----------2.0

2.8K-----------1.5

3K -----------1.0

Graphical representation of the above filter response is as shown in Figure (1).



Figure (1)

The magnitude corresponding to 3dB frequency is 5*0.707=3.535v. Note that the observed cutoff frequency is 2KHz, which is same as that of theoretically designed (In the frequency response list shown above shows 3.5v at cutoff frequency. In fact the value is 3.53 itself. But since on a CRO reading accuracy is limited by the ranging of voltage and error in reading the data, we have written the voltage value as 3.5; remember that it is not because the filter doesn’t exhibit exact cutoff frequency but we can’t read the response accurately).

2.4.6.SAMPLING FREQUENCY OF THE FILTER: - Sampling Frequency of the filter designed is 10KHz which implies that sampling time =1/10K=100ms.

Hence the looping part of the software should be completed within 100ms and has been achieved with just 83ms. To satisfy 100ms sampling time, delay is used. At the very beginning of the filter response there may be transient due to unsatisfied condition of sampling time and initial condition.

The discussion carried over the effect of sampling frequency variation and aliasing effect in earlier section also hold good here.

NOISE REJECTION ABILITY OF THE FILTER: - To study this, hardware setup is constructed as it is been constructed for I order Butterworth lowpass filter implementation.

Now our importance shifts to do a comparison of noise rejection capability of the I order and II order filter. There can’t be a second opinion about the performance of II order filter in eliminating the noise and thus making the signal ‘smoother’. Now our attention is drawn towards to have a trade-off between the performances of the filters.

Second order filters have sharper cutoff compared to first order filters, which is observed in this filter also. As per as noise is concerned both filters perform well.

LIMITATIONS: -

PIC Microcontrollers impose a lot of limitations in implementation of digital filters. Reader might be remembering that PIC MCU’s are 8-bit controllers having “Harvard Architecture” as its internal architecture. Those who wishes to study the digital filter response using PIC using PIC MCU’s as a tool are suggested to take notice of mentioned obstacles:

Processing of A/D converted data: - PIC 16F877 has a 10-bit built in internal ADC. The A/D converted data are stored in two 8-bit registers called ADRESL and ADRESH. The lower byte is stored in ADRESL and the remaining two higher bits are stored in ADRESH. Now the problem is, since to process this 10-bit A/D data it requires having 16-bit arithmetic operation, implementation, which in PIC 8-bit MCU, is a cumbersome job.

To overcome this problem care is taken when applying the input signal so that A/D converted data doesn’t exceed 8-bit or even it exceeds it should exceed the value by one bit only. All A/D converted bits are high when input is 5V.When input voltage is around 2.5V only lower bits of the A/D converted data are high. This is been tested by directly displaying the A/D converted data.

Now referring to DC shifter circuit in Figure (2.6b), the DC shift provided by the circuit is = -(1K W/6K W)*(VEE)

= -(1/6)*(-12V)

= 2V

But maximum input voltage level that can be applicable to get 8 bit A/D converted data is 2.5V

Therefore,

The voltage swing that can be applicable =2.5V-2V

= 0.5V

Thus the input signal to the PIC port pins can vary from 1.5V to 2.5V, 2V being DC value. Therefore for DC shifter, since there is already 2V DC shift provided by DC shifter, the maximum applicable input voltage is 1V.This is the reason why we have applied only 0.5 V input signal. If input level to DC shifter circuit exceeds 1V A/D converted data will exceed 8-bits which is processed by the software and hence even though the filter work according to the design, signal loses its original shape.

Sampling frequency limitation: - The time taken to complete single loop in final looping port of the software determines the sampling time. The first order Butterworth lowpass filter designed in our study used sampling frequency 0f 25KHz which implies sampling time = 40ms. Software routine written for any other, same or higher order filter utilize more than 40ms for its looping part. Hence with 4MHz clock frequency for the operation of PIC MCU, the maximum possible sampling frequency is 25KHz. Thus to get fairly good filtered and reconstructed signal, the maximum input signal frequency is applicable is around 10KHz. If higher clock frequency like 20MHz is used the A/D conversion speed is more. This saves time and hence sampling frequency can be higher to a little bit.

Floating-point arithmetic and –ve results: - Another major drawback of the PIC MCU is it doesn’t support floating-point arithmetic operations, which are very crucial aspects when we deal with digital filters. Owing to this reason floating point filter coefficients are truncated as well as scaled to an integer when we did this precautions are taken so that filter response does not change considerably beyond required designed response.

Truncated and scaled filter coefficients of lowpass filter have not much affected the filter characteristics. But for high pass and band pass/reject filters in addition to floating point arithmetic problems, -ve numbers also came into picture; processing of these –ve numbers and D/A conversion becomes another difficult job. Somehow floating point numbers can be handled, but playing with –ve numbers is certainly a tedious job.

The above floating problem can be overcome by using ‘PICLITE’ assembler, which is supported by MPLAB. By enabling the ‘PICLITE’ assembler we can write the program in C code as well as in assembly code. C codes are converted to assembly code by the assembler itself. These assembled codes can be programmed to PIC MCU.

References

1. “Digital Signal Processing” By Sanjit K.Mitra

2. “Digital Signal Processing” By P.Ramesh Babu

3. “Digital Filters” By T.J.Terrel and E.T.Powner

4. “BASIC Digital Signal Processing” By Gordon B. Lockart And Barry M.G.Cheetham

5. “Digital Signal Processing” By Alan V.Oppenheim And Ronald W.Schafer

6. “DSP Microprocessors: Advances and Automotive Applications” By Subra Ganeshan and Dr.Gopal Arvamudhan

7. PIC 16F87XA Data Sheet

8. Embedded Control Handbook-1994/95/Microchip

9. Microchip Technical Library CD-ROM-First Edition 2002

10. National Semiconductor CD-ROM-1995/96

11. “Design with PIC Microcontrollers” By John B.Peatman

12. “Opamps and Linear Integrated Circuits” By Ramakant A.Gayakwad

13. “Electronic Principles” By A.P.Malvino

www.mathworks.com

www.microchip.com

SRAM Chip Supporting Circuit Design

1 Introduction

Design of peripheral and supporting circuits such as sense amplifier, address decoders, precharge and I/O control circuits are very important for the proper functioning of SRAM. The memory cell has to be accessed by all these supporting circuits by the help of BL and BLbar lines. Address decoders select a particular cell for read/write operation. Address decoding delay account for the maximum part of the memory access time in addition to the delay provided by the bit line capacitances of the memory cell itself. Read and write circuits provide an interface between internal memory cells to the external hardware facilitating proper data transfer between them. Before any layout is designed for all these blocks they have to be tested for functionality and worst case possibilities to make them error free design.




2 Sense amplifiers

Since SRAM cells provide true differential outputs any differential configuration of sense amplifier is directly applied to SRAM design. One such type of configuration is shown in Figure (2.1). Sense amplifier is a latch formed by cross coupling two CMOS inverters. Sense enable (SE) signal is used to turn ON/OFF the sense amplifier BL and BLbar becomes I/O terminals of amplifier. During read operation, if cell had stored 1, then a small +ve voltage will develop between BL and BLbar with VBL>VBLbar. Then amplifier raises voltage VBL to VDD and VBLbar to 0V. This output is then directed to the chip I/O pin by the column decoder.



Figure (1) sense amplifier

Sense amplifier performs the following functions:

àAmplification: small bit line swings are resolved by the sense amplifier. This reduces power dissipation.

àReduction in delay: by accelerating the bit line transitions sense amplifier boosts the driving capability of the SRAM cell.

à Reduction in power dissipation: this is achieved by reducing large signal swing on the bit line eliminating the necessity to charge or discharge the bit line capacitance.

Simulation: SPICE simulation results of the sense amplifier for the schematic shown in Figure (1) is shown in Figure (2).



Figure (2) sense amplifier SPICE simulation waveform

Initially sense enable (SE) signal is deactivated. The inputs BL and BLbar lines are precharged and equalized to metastable point of the inverter. Initialization of read operation causes any one of the bit lines to drop. Once the sufficient amount of differential voltage is established SE signal is activated. The cross coupled inverters of the amplifier reaches to a stable operation point after the result of the positive feedback.

Sharing of the single sense amplifier between multiple columns can save area as well as power. Also by pulsing SE signal for short duration of evaluation reduces the static power the amplifier.

Normal W/L ratios are selected for NMOS and PMOS transistors. PMOS transistors have a W/L ratio of 6.66 which means that for 0.18 µ technology gate width of 1.2 µ. For NMOS transistors this ratio is 3.33 that are to say a gate width of 0.6 µ.

Simulation results are shown in Figure (2). Here sense amplifier is nothing but a differential amplifier. Node Y of the amplifier is forced with a pulse waveform. When the SE is activated, due to the differential configuration, BLbar shows complementary waveform of BL as shown by the circled area in simulation waveform. Further analysis is carried out along with SRAM cell and precharge circuits.

3 Precharge and Equalization Circuit

The precharge and equalization circuit is shown in Figure (3)



Figure (3) Precharge circuit and simulation setup

When precharge enable (PE) goes high prior to read operation, all three transistors conduct. M1 and M2 precharge the BL and BLbar to VDD/2. M3 helps to speed up this process by equalizing the initial voltages on the two lines. This equalization is critical to the proper operation of sense amplifier. Sense amplifier can erroneously interpret the any voltage difference present between BL and BLbar prior to the commencement of read operation.

Read operation sequence:

1. When precharge enable (PE) signal is made high both BL and BLbar precharges to VDD/2. Then PE is made low. This causes BL and BLbar to float for a small interval of time.

2. When word line is activated then voltage difference is established between BL and BLbar. If cell had stored 1, then VB>VBbar. If cell had stored 0, then VBBbar.

3. Now sense enable (SE) signal is activated. This turns ON the sense amplifier. Positive feedback structure of the sense amplifier establishes stable condition within a short time.

4 Half VDD generator

Half VDD sensing scheme has two advantages: it improves noise immunity and it has lower power consumption.



Figure (4) Half VDD generator

The basic circuit of half VDD generator consists of bias circuit and a driver circuit as shown in the Figure (4). The (W/L) ratio of the bias circuit transistors is set so that the voltage at the node B is VDD/2. Therefore voltage at node A is VDD/2+VTN (VTN-threshold voltage of NMOS transistor) and at node C is VDD/2-|VTP| (VTP-threshold voltage of PMOS transistor). The output voltage of the driver is stabilized at VDD/2. Static current of the driver circuit is very low due to poor ON state of driver transistors. Driver stage is in push pull configuration. (W/L) ratio of the driver transistors are made larger to suppress any unexpected change at the output node quickly by turning ON either transistor strongly.



Figure (5) half VDD generator SPICE simulation waveform

5 Address decoder circuits

Address decoder is required to select one of the 2M rows or columns in response to an M bit address input. A simple NOR based matrix structure fulfills this requirement. A 3x8 decoder used to decode 8 memory blocks is shown in the Figure (6). A PMOS is attached to each line. When there is no read write operations PEbar signal is kept high. Because of this arrangement the decoder circuit does not dissipate static power. NOR based decoders use less number of devices compared to normal decoder implementation methodology. Layout of such decoder is time consuming and cumbersome compared to NOR based implementation.

In the case of row decoder, PMOS is activated by precharge control signal PEbar prior to the address decoding process. All word line (WL) is pulled high to VDD during precharge. Column (or block) decoders have to provide the discharge path from the precharged bit line to the sense amplifier during read operation. The same lines should be able to drive the bit line to write either 0 or 1 to the memory SRAM cell. Read and write access time of the memory is primarily restricted by the propagation delay of the decoder. Floor plan of the decoder should be carefully studied before the layout implementation of the row and column decoders. Decoder outputs are connected throughout the memory cell making long interconnections which are main resources of delay and higher power consumption.

Generally NOR based decoders improves the speed of operation and achieve power efficiency. Larger the PMOS transistor, the faster is the pre-charging and so faster is the decoder. For 0.18 µ technology gate width of all NMOS transistors in both row and column decoders are selected as 0.6 µ. For PMOS transistors gate width is 1.2 µ.

5.1 Column decoder

In this SRAM design each block is connected as one column. Each block consists of 8 sub columns and 128 rows. BL and BLbar lines of the sub column have column enable transistors which are enabled or disabled by the output of 3x8 decoder.



Figure (6) 3x8 column decoder

At present buffer drivers for decoder outputs are not considered. But, due to the large capacitance offered by the column and row connections (more evident in row decoder) a buffer circuit may be necessary before the signal reaches column control transistors of each sub column.



Figure (7) 3x8 decoder SPICE simulation waveform

The SPICE simulation waveform is shown in Figure (7). Inputs A0 to A2 and complement of these are applied appropriately as per the NOR logic. (In the waveform all signals are named in small case). The outputs of the decoder C0 to C7 are highlighted by circles. False triggering of decoder output occurs due to the rise time and fall time of the address line signals. This can be counteracted by proper control of address inputs and DEbar signal.

5.2 Row decoder

7x128 row decoder schematic is extension of 3x8 decoder. The discussion on capacitance and false triggering holds good here as well. The corresponding SPICE simulation waveform is shown in Figure (8).



Figure (8) 7x128 row decoder: SPICE simulation waveform

Address inputs A3, A6 and A9 are shown in the waveform. Simulation waveforms of only six outputs out of 128 are shown. (In simulation waveform signals are named in small case). They are R0, R1, R63, R64, R126 and R127and are highlighted by the circles and arrows. For A3 A9 =0, R0 is selected and A3 to A9=127 R127 is selected.

6 I/O control circuits

I/O control circuits are integral part of the memory circuit. They interface internal memory cells with the external world. Generally internal operation of the cell runs in lower voltage range compared to the external world power supply of the chip. In such cases to resolve compatibility issues I/O circuits become essential. Here in this section read write circuits and buffer design for SRAM is presented.

6.1 Read buffer

Gate level and transistor level schematic is shown in Figure (9). Corresponding truth table of the circuit is listed in Table (1). Read enable (RE) signal is given as common input to two NAND gate while DL and DLbar becomes other two inputs for the gate. Push pull configuration of transistors finally drive the DIO line which is externally available for the chip. Basic NAND gate design strategy is used to design transistors. All the transistors of the NAND gate has common W/L ratio. PMOS transistor M8 and M10 of inverters have twice the width of M9 and M11.


Figure (8) 7x128 row decoder: SPICE simulation waveform

Address inputs A3, A6 and A9 are shown in the waveform. Simulation waveforms of only six outputs out of 128 are shown. (In simulation waveform signals are named in small case). They are R0, R1, R63, R64, R126 and R127and are highlighted by the circles and arrows. For A3 A9 =0, R0 is selected and A3 to A9=127 R127 is selected.

6 I/O control circuits

I/O control circuits are integral part of the memory circuit. They interface internal memory cells with the external world. Generally internal operation of the cell runs in lower voltage range compared to the external world power supply of the chip. In such cases to resolve compatibility issues I/O circuits become essential. Here in this section read write circuits and buffer design for SRAM is presented.

6.1 Read buffer

Gate level and transistor level schematic is shown in Figure (9). Corresponding truth table of the circuit is listed in Table (1). Read enable (RE) signal is given as common input to two NAND gate while DL and DLbar becomes other two inputs for the gate. Push pull configuration of transistors finally drive the DIO line which is externally available for the chip. Basic NAND gate design strategy is used to design transistors. All the transistors of the NAND gate has common W/L ratio. PMOS transistor M8 and M10 of inverters have twice the width of M9 and M11.





Table (1) read circuit truth table

Transistors M10 and M11 form driver circuit which interface to the DIO line of the chip. Power supply to this driver is directly given from the external power supply of the chip so that logic levels are compatible to the external interface unit.

6.2 Write circuit

Write circuit should be able to force the BL and BLbar line to change its state as per the given input data by charging the large bit line capacitances instantaneously. Hence write circuit is designed with NOR gates to provide higher current driving capability. Gate level and transistor level schematic is shown in Figure (10). The circuit resembles the read circuit with NAND gate replaced by NOR gates. Write enable (WE) signals control the write operation. Output of each NAND gate is driven by NMOS transistor having higher W/L ratio. These two transistors drive DL and DLbar lines and hence BL and BLbar lines. For the NMOS transistors of the NOR gate W/L ratio of 3.33 (i.e. W=0.6 µ) is selected and for PMOS transistors W/L ratio of 12 (i.e W=7.2 µ) is selected.W/L ratio for driving transistors M9 and M10 is selected to be 6.66 which makes gate width of 1.2 µ.





Table (2) write circuit truth table

6.3 Write buffer

Figure (11) write buffer-gate and transistor level

Write buffer shown in the Figure (11) is essential to interface DIO line to the write circuitry. External DIO line is given to the first inverter stage of buffer. Buffer draws power from internal power supply line VDD. Second stage output of buffer hence becomes compatible to internal logic levels of the chip.

7 Complete SRAM chip schematic

As we seen earlier complete SRAM has total 8 blocks and in each block cells are arranged in 128x8 matrix structure. Consider the Figure (12) wherein one block of memory is shown. Row select lines are given to R0 to R127 from row decoder output. Since whole block is considered as one column for parallel configuration of read and write operation, single column line activates individual sub column select transistors. Thus column decoder output C0 drives first block, C1 drives second block and so on till C7 drives 8th block. Row decoder output R0 to R127 is connected to all memory blocks.

Total 8 read and write circuits are sufficient for read and write operation. As shown in the Figure (12) read and write circuit I/Os are connected to BL and BLbar lines of sub columns. The read and write circuit connected to first sub column of first memory block, also connects to first sub column of second memory block, third memory block and so on. Similarly the second read write is connected to second sub column of all the blocks and this arrangement continues for all other sub columns of memory blocks. All these 8 set of read and write circuits are active at a given point of time to access any memory locations arranged in any row of any memory block which is decided by address decoders.




Figure (12) schematic of memory block

Access time difference of this parallel architecture and the architecture wherein individual memory bits are accessible, have to be studied. Nonetheless, in both architectures delay contributed by the address decoders play vital role. The overall switched capacitance can be reduced by dividing the word line into several sub word lines that are enabled while addressing. Similarly capacitances of bit line for every read-write operation can be reduced by partitioning of the memory.

8 Conclusions

Different supporting circuits like sense amplifier address decoders and I/O circuits are designed and analyzed by the help of SPICE simulation waveforms. Individual circuit performance is found to be satisfactory and its performance with the SRAM memory cell has been reported in the previous chapter. Quantitative analysis of all these circuits proved their functionalities. The range of difference voltage which sense amplifier can interpret original logic levels and time required to sense this difference has to be studied. Similarly capacitance and hence the delay offered by the decoder circuits to decode the input has to be analyzed. These will help in designing accurate layout of supporting circuits and thereby facilitating with the easy integration of these modules into the SRAM memory layout.

Bibliography

[1] Sung Mo Kang and Yusuf Leblebici, CMOS digital integrated circuits-analysis and design, Tata McGraw hill, third edition, 2003

[2] Jan M Rabaey & Anantha Chandrakasan & Borivoje Nikolic, Digital integrated circuits-a design perspective, Pearson education, third edition, 2005

[3] Sedra & smith, Microelectronic circuits, oxford university press, fifth edition, 2004

Appendix

*Model files

* Predictive Technology Model Beta Version

* 180nm NMOS SPICE Parametersv (normal one)

*

.model NMOS nmos

+Level = 49

+Lint = 4.e-08 Tox = 4.e-09

+Vth0 = 0.3999 Rdsw = 250

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1

+Xj= 6.0000000E-08 Nch= 5.9500000E+17

+lln= 1.0000000 lwn= 1.0000000 wln= 0.00

+wwn= 0.00 ll= 0.00

+lw= 0.00 lwl= 0.00 wint= 0.00

+wl= 0.00 ww= 0.00 wwl= 0.00

+Mobmod= 1 binunit= 2 xl= 0

+xw= 0 binflag= 0

+Dwg= 0.00 Dwb= 0.00

+K1= 0.5613000 K2= 1.0000000E-02

+K3= 0.00 Dvt0= 8.0000000 Dvt1= 0.7500000

+Dvt2= 8.0000000E-03 Dvt0w= 0.00 Dvt1w= 0.00

+Dvt2w= 0.00 Nlx= 1.6500000E-07 W0= 0.00

+K3b= 0.00 Ngate= 5.0000000E+20

+Vsat= 1.3800000E+05 Ua= -7.0000000E-10 Ub= 3.5000000E-18

+Uc= -5.2500000E-11 Prwb= 0.00

+Prwg= 0.00 Wr= 1.0000000 U0= 3.5000000E-02

+A0= 1.1000000 Keta= 4.0000000E-02 A1= 0.00

+A2= 1.0000000 Ags= -1.0000000E-02 B0= 0.00

+B1= 0.00

+Voff= -0.12350000 NFactor= 0.9000000 Cit= 0.00

+Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00

+Eta0= 0.2200000 Etab= 0.00 Dsub= 0.8000000

+Pclm= 5.0000000E-02 Pdiblc1= 1.2000000E-02 Pdiblc2= 7.5000000E-03

+Pdiblcb= -1.3500000E-02 Drout= 1.7999999E-02 Pscbe1= 8.6600000E+08

+Pscbe2= 1.0000000E-20 Pvag= -0.2800000 Delta= 1.0000000E-02

+Alpha0= 0.00 Beta0= 30.0000000

+kt1= -0.3700000 kt2= -4.0000000E-02 At= 5.5000000E+04

+Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1= -3.3473000E-19

+Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00

+Cj= 0.00365 Mj= 0.54 Pb= 0.982

+Cjsw= 7.9E-10 Mjsw= 0.31 Php= 0.841

+Cta= 0 Ctp= 0 Pta= 0

+Ptp= 0 JS=1.50E-08 JSW=2.50E-13

+N=1.0 Xti=3.0 Cgdo=2.786E-10

+Cgso=2.786E-10 Cgbo=0.0E+00 Capmod= 2

+NQSMOD= 0 Elm= 5 Xpart= 1

+Cgsl= 1.6E-10 Cgdl= 1.6E-10 Ckappa= 2.886

+Cf= 1.069e-10 Clc= 0.0000001 Cle= 0.6

+Dlc= 4E-08 Dwc= 0 Vfbcv= -1

*

* Predictive Technology Model Beta Version

* 180nm PMOS SPICE Parametersv (normal one)

*

.model PMOS pmos

+Level = 49

+Lint = 3.e-08 Tox = 4.2e-09

+Vth0 = -0.42 Rdsw = 450

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1

+Xj= 7.0000000E-08 Nch= 5.9200000E+17

+lln= 1.0000000 lwn= 1.0000000 wln= 0.00

+wwn= 0.00 ll= 0.00

+lw= 0.00 lwl= 0.00 wint= 0.00

+wl= 0.00 ww= 0.00 wwl= 0.00

+Mobmod= 1 binunit= 2 xl= 0.00

+xw= 0.00

+binflag= 0 Dwg= 0.00 Dwb= 0.00

+ACM= 0 ldif=0.00 hdif=0.00

+rsh= 0 rd= 0 rs= 0

+rsc= 0 rdc= 0

+K1= 0.5560000 K2= 0.00

+K3= 0.00 Dvt0= 11.2000000 Dvt1= 0.7200000

+Dvt2= -1.0000000E-02 Dvt0w= 0.00 Dvt1w= 0.00

+Dvt2w= 0.00 Nlx= 9.5000000E-08 W0= 0.00

+K3b= 0.00 Ngate= 5.0000000E+20

+Vsat= 1.0500000E+05 Ua= -1.2000000E-10 Ub= 1.0000000E-18

+Uc= -2.9999999E-11 Prwb= 0.00

+Prwg= 0.00 Wr= 1.0000000 U0= 8.0000000E-03

+A0= 2.1199999 Keta= 2.9999999E-02 A1= 0.00

+A2= 0.4000000 Ags= -0.1000000 B0= 0.00

+B1= 0.00

+Voff= -6.40000000E-02 NFactor= 1.4000000 Cit= 0.00

+Cdsc= 0.00 Cdscb= 0.00 Cdscd= 0.00

+Eta0= 8.5000000 Etab= 0.00 Dsub= 2.8000000

+Pclm= 2.0000000 Pdiblc1= 0.1200000 Pdiblc2= 8.0000000E-05

+Pdiblcb= 0.1450000 Drout= 5.0000000E-02 Pscbe1= 1.0000000E-20

+Pscbe2= 1.0000000E-20 Pvag= -6.0000000E-02 Delta= 1.0000000E-02

+Alpha0= 0.00 Beta0= 30.0000000

+kt1= -0.3700000 kt2= -4.0000000E-02 At= 5.5000000E+04

+Ute= -1.4800000 Ua1= 9.5829000E-10 Ub1= -3.3473000E-19

+Uc1= 0.00 Kt1l= 4.0000000E-09 Prt= 0.00

+Cj= 0.00138 Mj= 1.05 Pb= 1.24

+Cjsw= 1.44E-09 Mjsw= 0.43 Php= 0.841

+Cta= 0.00093 Ctp= 0 Pta= 0.00153

+Ptp= 0 JS=1.50E-08 JSW=2.50E-13

+N=1.0 Xti=3.0 Cgdo=2.786E-10

+Cgso=2.786E-10 Cgbo=0.0E+00 Capmod= 2

+NQSMOD= 0 Elm= 5 Xpart= 1

+Cgsl= 1.6E-10 Cgdl= 1.6E-10 Ckappa= 2.886

+Cf= 1.058e-10 Clc= 0.0000001 Cle= 0.6

+Dlc= 3E-08 Dwc= 0 Vfbcv= -1

==============================================================

*SPICE code for 3x8 decoder

*=======================

.include "C:\Program Files\LTC\SwCADIII\lib\cmp\180nm_model.txt"

*=========================

*.subckt inverter in out vdd

*m11 out in vdd vdd pmos L=0.18u W=1.2u

*m22 out in gnd gnd nmos L=0.18u W=0.6u

*.ends

*======================================

m1 c0 a2 gnd gnd nmos L=0.18u W=0.6u

m2 c0 a1 gnd gnd nmos L=0.18u W=0.6u

m3 c0 a0 gnd gnd nmos L=0.18u W=0.6u

m4 c1 a2 gnd gnd nmos L=0.18u W=0.6u

m5 c1 a1 gnd gnd nmos L=0.18u W=0.6u

m6 c1 a0bar gnd gnd nmos L=0.18u W=0.6u

m7 c2 a2 gnd gnd nmos L=0.18u W=0.6u

m8 c2 a1bar gnd gnd nmos L=0.18u W=0.6u

m9 c2 a0 gnd gnd nmos L=0.18u W=0.6u

m10 c3 a2 gnd gnd nmos L=0.18u W=0.6u

m11 c3 a1bar gnd gnd nmos L=0.18u W=0.6u

m12 c3 a0bar gnd gnd nmos L=0.18u W=0.6u

m13 c4 a2bar gnd gnd nmos L=0.18u W=0.6u

m14 c4 a1 gnd gnd nmos L=0.18u W=0.6u

m15 c4 a0 gnd gnd nmos L=0.18u W=0.6u

m16 c5 a2bar gnd gnd nmos L=0.18u W=0.6u

m17 c5 a1 gnd gnd nmos L=0.18u W=0.6u

m18 c5 a0bar gnd gnd nmos L=0.18u W=0.6u

m19 c6 a2bar gnd gnd nmos L=0.18u W=0.6u

m20 c6 a1bar gnd gnd nmos L=0.18u W=0.6u

m21 c6 a0 gnd gnd nmos L=0.18u W=0.6u

m22 c7 a2bar gnd gnd nmos L=0.18u W=0.6u

m23 c7 a1bar gnd gnd nmos L=0.18u W=0.6u

m24 c7 a0bar gnd gnd nmos L=0.18u W=0.6u

*===========================================

m25 c0 DEbar vdd vdd pmos L=0.18u W=1.2u

m26 c1 DEbar vdd vdd pmos L=0.18u W=1.2u

m27 c2 DEbar vdd vdd pmos L=0.18u W=1.2u

m28 c3 DEbar vdd vdd pmos L=0.18u W=1.2u

m29 c4 DEbar vdd vdd pmos L=0.18u W=1.2u

m30 c5 DEbar vdd vdd pmos L=0.18u W=1.2u

m31 c6 DEbar vdd vdd pmos L=0.18u W=1.2u

m32 c7 DEbar vdd vdd pmos L=0.18u W=1.2u

*====================================

*xnot0 a0 a0bar vdd inverter

*xnot1 a1 a1bar vdd inverter

*xnot2 a2 a2bar vdd inverter

*=====================================

m33 a2bar a2 vdd vdd pmos L=0.18u W=1.2u

m34 a2bar a2 gnd gnd nmos L=0.18u W=0.6u

m35 a1bar a1 vdd vdd pmos L=0.18u W=1.2u

m36 a1bar a1 gnd gnd nmos L=0.18u W=0.6u

m37 a0bar a0 vdd vdd pmos L=0.18u W=1.2u

m38 a0bar a0 gnd gnd nmos L=0.18u W=0.6u

*====================================

vvdd vdd gnd dc 1.8v

*vDEbar DEbar gnd dc 1.8

vDEbar DEbar gnd pulse(0 1.8 1n 1n 1n 40n 80n)

va0 a0 gnd pulse(1.8 0 1n 1n 1n 5n 10n)

va1 a1 gnd pulse(1.8 0 1n 1n 1n 10n 20n)

va2 a2 gnd pulse(1.8 0 1n 1n 1n 20n 40n)

*=====================================

.tran 0 200n

.plot tran v(a0) v(a0bar) v(a1) v(a1bar) v(a2) v(a2bar) v(c0) v(c1) v(c2) v(c3) v(c4) v(c5) v(c6) v(c7)

.end

===============================================================

*7x128 decoder

*working !!!

*=======================

.include "C:\Program Files\LTC\SwCADIII\lib\cmp\180nm_model.txt"

*=========================

*.subckt inverter in out vdd

*m11 out in vdd vdd pmos L=0.18u W=1.2u

*m22 out in gnd gnd nmos L=0.18u W=0.6u

*.ends

*======================================

m1 r0 a9 gnd gnd nmos L=0.18u W=0.6u

m2 r0 a8 gnd gnd nmos L=0.18u W=0.6u

m3 r0 a7 gnd gnd nmos L=0.18u W=0.6u

m4 r0 a6 gnd gnd nmos L=0.18u W=0.6u

m5 r0 a5 gnd gnd nmos L=0.18u W=0.6u

m6 r0 a4 gnd gnd nmos L=0.18u W=0.6u

m7 r0 a3 gnd gnd nmos L=0.18u W=0.6u

m8 r1 a9 gnd gnd nmos L=0.18u W=0.6u

m9 r1 a8 gnd gnd nmos L=0.18u W=0.6u

m10 r1 a7 gnd gnd nmos L=0.18u W=0.6u

m11 r1 a6 gnd gnd nmos L=0.18u W=0.6u

m12 r1 a5 gnd gnd nmos L=0.18u W=0.6u

m13 r1 a4 gnd gnd nmos L=0.18u W=0.6u

m14 r1 a3bar gnd gnd nmos L=0.18u W=0.6u

m15 r2 a9 gnd gnd nmos L=0.18u W=0.6u

m16 r2 a8 gnd gnd nmos L=0.18u W=0.6u

m17 r2 a7 gnd gnd nmos L=0.18u W=0.6u

m18 r2 a6 gnd gnd nmos L=0.18u W=0.6u

m19 r2 a5 gnd gnd nmos L=0.18u W=0.6u

m20 r2 a4bar gnd gnd nmos L=0.18u W=0.6u

m21 r2 a3 gnd gnd nmos L=0.18u W=0.6u

m22 r3 a9 gnd gnd nmos L=0.18u W=0.6u

m23 r3 a8 gnd gnd nmos L=0.18u W=0.6u

m24 r3 a7 gnd gnd nmos L=0.18u W=0.6u

m25 r3 a6 gnd gnd nmos L=0.18u W=0.6u

m26 r3 a5 gnd gnd nmos L=0.18u W=0.6u

m27 r3 a4bar gnd gnd nmos L=0.18u W=0.6u

m28 r3 a3bar gnd gnd nmos L=0.18u W=0.6u

m29 r4 a9 gnd gnd nmos L=0.18u W=0.6u

m30 r4 a8 gnd gnd nmos L=0.18u W=0.6u

m31 r4 a7 gnd gnd nmos L=0.18u W=0.6u

m32 r4 a6 gnd gnd nmos L=0.18u W=0.6u

m33 r4 a5bar gnd gnd nmos L=0.18u W=0.6u

m34 r4 a4 gnd gnd nmos L=0.18u W=0.6u

m35 r4 a3 gnd gnd nmos L=0.18u W=0.6u

m36 r5 a9 gnd gnd nmos L=0.18u W=0.6u

m37 r5 a8 gnd gnd nmos L=0.18u W=0.6u

m38 r5 a7 gnd gnd nmos L=0.18u W=0.6u

m39 r5 a6 gnd gnd nmos L=0.18u W=0.6u

m40 r5 a5bar gnd gnd nmos L=0.18u W=0.6u

m41 r5 a4 gnd gnd nmos L=0.18u W=0.6u

m42 r5 a3bar gnd gnd nmos L=0.18u W=0.6u

m43 r6 a9 gnd gnd nmos L=0.18u W=0.6u

m44 r6 a8 gnd gnd nmos L=0.18u W=0.6u

m45 r6 a7 gnd gnd nmos L=0.18u W=0.6u

m46 r6 a6 gnd gnd nmos L=0.18u W=0.6u

m47 r6 a5bar gnd gnd nmos L=0.18u W=0.6u

m48 r6 a4bar gnd gnd nmos L=0.18u W=0.6u

m49 r6 a3 gnd gnd nmos L=0.18u W=0.6u

m50 r7 a9 gnd gnd nmos L=0.18u W=0.6u

m51 r7 a8 gnd gnd nmos L=0.18u W=0.6u

m52 r7 a7 gnd gnd nmos L=0.18u W=0.6u

m53 r7 a6 gnd gnd nmos L=0.18u W=0.6u

m54 r7 a5bar gnd gnd nmos L=0.18u W=0.6u

m55 r7 a4bar gnd gnd nmos L=0.18u W=0.6u

m56 r7 a3bar gnd gnd nmos L=0.18u W=0.6u

m57 r8 a9 gnd gnd nmos L=0.18u W=0.6u

m58 r8 a8 gnd gnd nmos L=0.18u W=0.6u

m59 r8 a7 gnd gnd nmos L=0.18u W=0.6u

m60 r8 a6bar gnd gnd nmos L=0.18u W=0.6u

m61 r8 a5 gnd gnd nmos L=0.18u W=0.6u

m62 r8 a4 gnd gnd nmos L=0.18u W=0.6u

m63 r8 a3 gnd gnd nmos L=0.18u W=0.6u

m64 r9 a9 gnd gnd nmos L=0.18u W=0.6u

m65 r9 a8 gnd gnd nmos L=0.18u W=0.6u

m66 r9 a7 gnd gnd nmos L=0.18u W=0.6u

m67 r9 a6bar gnd gnd nmos L=0.18u W=0.6u

m68 r9 a5 gnd gnd nmos L=0.18u W=0.6u

m69 r9 a4 gnd gnd nmos L=0.18u W=0.6u

m70 r9 a3bar gnd gnd nmos L=0.18u W=0.6u

m71 r10 a9 gnd gnd nmos L=0.18u W=0.6u

m72 r10 a8 gnd gnd nmos L=0.18u W=0.6u

m73 r10 a7 gnd gnd nmos L=0.18u W=0.6u

m74 r10 a6bar gnd gnd nmos L=0.18u W=0.6u

m75 r10 a5 gnd gnd nmos L=0.18u W=0.6u

m76 r10 a4bar gnd gnd nmos L=0.18u W=0.6u

m77 r10 a3 gnd gnd nmos L=0.18u W=0.6u

m78 r11 a9 gnd gnd nmos L=0.18u W=0.6u

m79 r11 a8 gnd gnd nmos L=0.18u W=0.6u

m80 r11 a7 gnd gnd nmos L=0.18u W=0.6u

m81 r11 a6bar gnd gnd nmos L=0.18u W=0.6u

m82 r11 a5 gnd gnd nmos L=0.18u W=0.6u

m83 r11 a4bar gnd gnd nmos L=0.18u W=0.6u

m84 r11 a3bar gnd gnd nmos L=0.18u W=0.6u

m85 r12 a9 gnd gnd nmos L=0.18u W=0.6u

m86 r12 a8 gnd gnd nmos L=0.18u W=0.6u

m87 r12 a7 gnd gnd nmos L=0.18u W=0.6u

m88 r12 a6bar gnd gnd nmos L=0.18u W=0.6u

m89 r12 a5bar gnd gnd nmos L=0.18u W=0.6u

m90 r12 a4 gnd gnd nmos L=0.18u W=0.6u

m91 r12 a3 gnd gnd nmos L=0.18u W=0.6u

m92 r13 a9 gnd gnd nmos L=0.18u W=0.6u

m93 r13 a8 gnd gnd nmos L=0.18u W=0.6u

m94 r13 a7 gnd gnd nmos L=0.18u W=0.6u

m95 r13 a6bar gnd gnd nmos L=0.18u W=0.6u

m96 r13 a5bar gnd gnd nmos L=0.18u W=0.6u

m97 r13 a4 gnd gnd nmos L=0.18u W=0.6u

m98 r13 a3bar gnd gnd nmos L=0.18u W=0.6u

m99 r14 a9 gnd gnd nmos L=0.18u W=0.6u

m100 r14 a8 gnd gnd nmos L=0.18u W=0.6u

m101 r14 a7 gnd gnd nmos L=0.18u W=0.6u

m102 r14 a6bar gnd gnd nmos L=0.18u W=0.6u

m103 r14 a5bar gnd gnd nmos L=0.18u W=0.6u

m104 r14 a4bar gnd gnd nmos L=0.18u W=0.6u

m105 r14 a3 gnd gnd nmos L=0.18u W=0.6u

m106 r15 a9 gnd gnd nmos L=0.18u W=0.6u

m107 r15 a8 gnd gnd nmos L=0.18u W=0.6u

m108 r15 a7 gnd gnd nmos L=0.18u W=0.6u

m109 r15 a6bar gnd gnd nmos L=0.18u W=0.6u

m110 r15 a5bar gnd gnd nmos L=0.18u W=0.6u

m111 r15 a4bar gnd gnd nmos L=0.18u W=0.6u

m112 r15 a3bar gnd gnd nmos L=0.18u W=0.6u

m113 r16 a9 gnd gnd nmos L=0.18u W=0.6u

m114 r16 a8 gnd gnd nmos L=0.18u W=0.6u

m115 r16 a7bar gnd gnd nmos L=0.18u W=0.6u

m116 r16 a6 gnd gnd nmos L=0.18u W=0.6u

m117 r16 a5 gnd gnd nmos L=0.18u W=0.6u

m118 r16 a4 gnd gnd nmos L=0.18u W=0.6u

m119 r16 a3 gnd gnd nmos L=0.18u W=0.6u

m120 r17 a9 gnd gnd nmos L=0.18u W=0.6u

m121 r17 a8 gnd gnd nmos L=0.18u W=0.6u

m122 r17 a7bar gnd gnd nmos L=0.18u W=0.6u

m123 r17 a6 gnd gnd nmos L=0.18u W=0.6u

m124 r17 a5 gnd gnd nmos L=0.18u W=0.6u

m125 r17 a4 gnd gnd nmos L=0.18u W=0.6u

m126 r17 a3bar gnd gnd nmos L=0.18u W=0.6u

m127 r18 a9 gnd gnd nmos L=0.18u W=0.6u

m128 r18 a8 gnd gnd nmos L=0.18u W=0.6u

m129 r18 a7bar gnd gnd nmos L=0.18u W=0.6u

m130 r18 a6 gnd gnd nmos L=0.18u W=0.6u

m131 r18 a5 gnd gnd nmos L=0.18u W=0.6u

m132 r18 a4bar gnd gnd nmos L=0.18u W=0.6u

m133 r18 a3 gnd gnd nmos L=0.18u W=0.6u

m134 r19 a9 gnd gnd nmos L=0.18u W=0.6u

m135 r19 a8 gnd gnd nmos L=0.18u W=0.6u

m136 r19 a7bar gnd gnd nmos L=0.18u W=0.6u

m137 r19 a6 gnd gnd nmos L=0.18u W=0.6u

m138 r19 a5 gnd gnd nmos L=0.18u W=0.6u

m139 r19 a4bar gnd gnd nmos L=0.18u W=0.6u

m140 r19 a3bar gnd gnd nmos L=0.18u W=0.6u

m141 r20 a9 gnd gnd nmos L=0.18u W=0.6u

m142 r20 a8 gnd gnd nmos L=0.18u W=0.6u

m143 r20 a7bar gnd gnd nmos L=0.18u W=0.6u

m144 r20 a6 gnd gnd nmos L=0.18u W=0.6u

m145 r20 a5bar gnd gnd nmos L=0.18u W=0.6u

m146 r20 a4 gnd gnd nmos L=0.18u W=0.6u

m147 r20 a3 gnd gnd nmos L=0.18u W=0.6u

m148 r21 a9 gnd gnd nmos L=0.18u W=0.6u

m149 r21 a8 gnd gnd nmos L=0.18u W=0.6u

m150 r21 a7bar gnd gnd nmos L=0.18u W=0.6u

m151 r21 a6 gnd gnd nmos L=0.18u W=0.6u

m152 r21 a5bar gnd gnd nmos L=0.18u W=0.6u

m153 r21 a4 gnd gnd nmos L=0.18u W=0.6u

m154 r21 a3bar gnd gnd nmos L=0.18u W=0.6u

m155 r22 a9 gnd gnd nmos L=0.18u W=0.6u

m156 r22 a8 gnd gnd nmos L=0.18u W=0.6u

m157 r22 a7bar gnd gnd nmos L=0.18u W=0.6u

m158 r22 a6 gnd gnd nmos L=0.18u W=0.6u

m159 r22 a5bar gnd gnd nmos L=0.18u W=0.6u

m160 r22 a4bar gnd gnd nmos L=0.18u W=0.6u

m161 r22 a3 gnd gnd nmos L=0.18u W=0.6u

m162 r23 a9 gnd gnd nmos L=0.18u W=0.6u

m163 r23 a8 gnd gnd nmos L=0.18u W=0.6u

m164 r23 a7bar gnd gnd nmos L=0.18u W=0.6u

m165 r23 a6 gnd gnd nmos L=0.18u W=0.6u

m166 r23 a5bar gnd gnd nmos L=0.18u W=0.6u

m167 r23 a4bar gnd gnd nmos L=0.18u W=0.6u

m168 r23 a3bar gnd gnd nmos L=0.18u W=0.6u

m169 r24 a9 gnd gnd nmos L=0.18u W=0.6u

m170 r24 a8 gnd gnd nmos L=0.18u W=0.6u

m171 r24 a7bar gnd gnd nmos L=0.18u W=0.6u

m172 r24 a6bar gnd gnd nmos L=0.18u W=0.6u

m173 r24 a5 gnd gnd nmos L=0.18u W=0.6u

m174 r24 a4 gnd gnd nmos L=0.18u W=0.6u

m175 r24 a3 gnd gnd nmos L=0.18u W=0.6u

m176 r25 a9 gnd gnd nmos L=0.18u W=0.6u

m177 r25 a8 gnd gnd nmos L=0.18u W=0.6u

m178 r25 a7bar gnd gnd nmos L=0.18u W=0.6u

m179 r25 a6bar gnd gnd nmos L=0.18u W=0.6u

m180 r25 a5 gnd gnd nmos L=0.18u W=0.6u

m181 r25 a4 gnd gnd nmos L=0.18u W=0.6u

m182 r25 a3bar gnd gnd nmos L=0.18u W=0.6u

m183 r26 a9 gnd gnd nmos L=0.18u W=0.6u

m184 r26 a8 gnd gnd nmos L=0.18u W=0.6u

m185 r26 a7bar gnd gnd nmos L=0.18u W=0.6u

m186 r26 a6bar gnd gnd nmos L=0.18u W=0.6u

m187 r26 a5 gnd gnd nmos L=0.18u W=0.6u

m188 r26 a4bar gnd gnd nmos L=0.18u W=0.6u

m189 r26 a3 gnd gnd nmos L=0.18u W=0.6u

m190 r27 a9 gnd gnd nmos L=0.18u W=0.6u

m191 r27 a8 gnd gnd nmos L=0.18u W=0.6u

m192 r27 a7bar gnd gnd nmos L=0.18u W=0.6u

m193 r27 a6bar gnd gnd nmos L=0.18u W=0.6u

m194 r27 a5 gnd gnd nmos L=0.18u W=0.6u

m195 r27 a4bar gnd gnd nmos L=0.18u W=0.6u

m196 r27 a3bar gnd gnd nmos L=0.18u W=0.6u

m197 r28 a9 gnd gnd nmos L=0.18u W=0.6u

m198 r28 a8 gnd gnd nmos L=0.18u W=0.6u

m199 r28 a7bar gnd gnd nmos L=0.18u W=0.6u

m200 r28 a6bar gnd gnd nmos L=0.18u W=0.6u

m201 r28 a5bar gnd gnd nmos L=0.18u W=0.6u

m202 r28 a4 gnd gnd nmos L=0.18u W=0.6u

m203 r28 a3 gnd gnd nmos L=0.18u W=0.6u

m204 r29 a9 gnd gnd nmos L=0.18u W=0.6u

m205 r29 a8 gnd gnd nmos L=0.18u W=0.6u

m206 r29 a7bar gnd gnd nmos L=0.18u W=0.6u

m207 r29 a6bar gnd gnd nmos L=0.18u W=0.6u

m208 r29 a5bar gnd gnd nmos L=0.18u W=0.6u

m209 r29 a4 gnd gnd nmos L=0.18u W=0.6u

m210 r29 a3bar gnd gnd nmos L=0.18u W=0.6u

m211 r30 a9 gnd gnd nmos L=0.18u W=0.6u

m212 r30 a8 gnd gnd nmos L=0.18u W=0.6u

m213 r30 a7bar gnd gnd nmos L=0.18u W=0.6u

m214 r30 a6bar gnd gnd nmos L=0.18u W=0.6u

m215 r30 a5bar gnd gnd nmos L=0.18u W=0.6u

m216 r30 a4bar gnd gnd nmos L=0.18u W=0.6u

m217 r30 a3 gnd gnd nmos L=0.18u W=0.6u

m218 r31 a9 gnd gnd nmos L=0.18u W=0.6u

m219 r31 a8 gnd gnd nmos L=0.18u W=0.6u

m220 r31 a7bar gnd gnd nmos L=0.18u W=0.6u

m221 r31 a6bar gnd gnd nmos L=0.18u W=0.6u

m222 r31 a5bar gnd gnd nmos L=0.18u W=0.6u

m223 r31 a4bar gnd gnd nmos L=0.18u W=0.6u

m224 r31 a3bar gnd gnd nmos L=0.18u W=0.6u

m225 r32 a9 gnd gnd nmos L=0.18u W=0.6u

m226 r32 a8bar gnd gnd nmos L=0.18u W=0.6u

m227 r32 a7 gnd gnd nmos L=0.18u W=0.6u

m228 r32 a6 gnd gnd nmos L=0.18u W=0.6u

m229 r32 a5 gnd gnd nmos L=0.18u W=0.6u

m230 r32 a4 gnd gnd nmos L=0.18u W=0.6u

m231 r32 a3 gnd gnd nmos L=0.18u W=0.6u

m232 r33 a9 gnd gnd nmos L=0.18u W=0.6u

m233 r33 a8bar gnd gnd nmos L=0.18u W=0.6u

m234 r33 a7 gnd gnd nmos L=0.18u W=0.6u

m235 r33 a6 gnd gnd nmos L=0.18u W=0.6u

m236 r33 a5 gnd gnd nmos L=0.18u W=0.6u

m237 r33 a4 gnd gnd nmos L=0.18u W=0.6u

m238 r33 a3bar gnd gnd nmos L=0.18u W=0.6u

m239 r34 a9 gnd gnd nmos L=0.18u W=0.6u

m240 r34 a8bar gnd gnd nmos L=0.18u W=0.6u

m241 r34 a7 gnd gnd nmos L=0.18u W=0.6u

m242 r34 a6 gnd gnd nmos L=0.18u W=0.6u

m243 r34 a5 gnd gnd nmos L=0.18u W=0.6u

m244 r34 a4bar gnd gnd nmos L=0.18u W=0.6u

m245 r34 a3 gnd gnd nmos L=0.18u W=0.6u

m246 r35 a9 gnd gnd nmos L=0.18u W=0.6u

m247 r35 a8bar gnd gnd nmos L=0.18u W=0.6u

m248 r35 a7 gnd gnd nmos L=0.18u W=0.6u

m249 r35 a6 gnd gnd nmos L=0.18u W=0.6u

m250 r35 a5 gnd gnd nmos L=0.18u W=0.6u

m251 r35 a4bar gnd gnd nmos L=0.18u W=0.6u

m252 r35 a3bar gnd gnd nmos L=0.18u W=0.6u

m253 r36 a9 gnd gnd nmos L=0.18u W=0.6u

m254 r36 a8bar gnd gnd nmos L=0.18u W=0.6u

m255 r36 a7 gnd gnd nmos L=0.18u W=0.6u

m256 r36 a6 gnd gnd nmos L=0.18u W=0.6u

m257 r36 a5bar gnd gnd nmos L=0.18u W=0.6u

m258 r36 a4 gnd gnd nmos L=0.18u W=0.6u

m259 r36 a3 gnd gnd nmos L=0.18u W=0.6u

m260 r37 a9 gnd gnd nmos L=0.18u W=0.6u

m261 r37 a8bar gnd gnd nmos L=0.18u W=0.6u

m262 r37 a7 gnd gnd nmos L=0.18u W=0.6u

m263 r37 a6 gnd gnd nmos L=0.18u W=0.6u

m264 r37 a5bar gnd gnd nmos L=0.18u W=0.6u

m265 r37 a4 gnd gnd nmos L=0.18u W=0.6u

m266 r37 a3bar gnd gnd nmos L=0.18u W=0.6u

m267 r38 a9 gnd gnd nmos L=0.18u W=0.6u

m268 r38 a8bar gnd gnd nmos L=0.18u W=0.6u

m269 r38 a7 gnd gnd nmos L=0.18u W=0.6u

m270 r38 a6 gnd gnd nmos L=0.18u W=0.6u

m271 r38 a5bar gnd gnd nmos L=0.18u W=0.6u

m272 r38 a4bar gnd gnd nmos L=0.18u W=0.6u

m273 r38 a3 gnd gnd nmos L=0.18u W=0.6u

m274 r39 a9 gnd gnd nmos L=0.18u W=0.6u

m275 r39 a8bar gnd gnd nmos L=0.18u W=0.6u

m276 r39 a7 gnd gnd nmos L=0.18u W=0.6u

m277 r39 a6 gnd gnd nmos L=0.18u W=0.6u

m278 r39 a5bar gnd gnd nmos L=0.18u W=0.6u

m279 r39 a4bar gnd gnd nmos L=0.18u W=0.6u

m280 r39 a3bar gnd gnd nmos L=0.18u W=0.6u

m281 r40 a9 gnd gnd nmos L=0.18u W=0.6u

m282 r40 a8bar gnd gnd nmos L=0.18u W=0.6u

m283 r40 a7 gnd gnd nmos L=0.18u W=0.6u

m284 r40 a6bar gnd gnd nmos L=0.18u W=0.6u

m285 r40 a5 gnd gnd nmos L=0.18u W=0.6u

m286 r40 a4 gnd gnd nmos L=0.18u W=0.6u

m287 r40 a3 gnd gnd nmos L=0.18u W=0.6u

m288 r41 a9 gnd gnd nmos L=0.18u W=0.6u

m289 r41 a8bar gnd gnd nmos L=0.18u W=0.6u

m290 r41 a7 gnd gnd nmos L=0.18u W=0.6u

m291 r41 a6bar gnd gnd nmos L=0.18u W=0.6u

m292 r41 a5 gnd gnd nmos L=0.18u W=0.6u

m293 r41 a4 gnd gnd nmos L=0.18u W=0.6u

m294 r41 a3bar gnd gnd nmos L=0.18u W=0.6u

m295 r42 a9 gnd gnd nmos L=0.18u W=0.6u

m296 r42 a8bar gnd gnd nmos L=0.18u W=0.6u

m297 r42 a7 gnd gnd nmos L=0.18u W=0.6u

m298 r42 a6bar gnd gnd nmos L=0.18u W=0.6u

m299 r42 a5 gnd gnd nmos L=0.18u W=0.6u

m300 r42 a4bar gnd gnd nmos L=0.18u W=0.6u

m301 r42 a3 gnd gnd nmos L=0.18u W=0.6u

*============================================

*==========================================

*===========================================

m302 r43 a9 gnd gnd nmos L=0.18u W=0.6u

m303 r43 a8bar gnd gnd nmos L=0.18u W=0.6u

m304 r43 a7 gnd gnd nmos L=0.18u W=0.6u

m305 r43 a6bar gnd gnd nmos L=0.18u W=0.6u

m306 r43 a5 gnd gnd nmos L=0.18u W=0.6u

m307 r43 a4bar gnd gnd nmos L=0.18u W=0.6u

m308 r43 a3bar gnd gnd nmos L=0.18u W=0.6u

m309 r44 a9 gnd gnd nmos L=0.18u W=0.6u

m310 r44 a8bar gnd gnd nmos L=0.18u W=0.6u

m311 r44 a7 gnd gnd nmos L=0.18u W=0.6u

m312 r44 a6bar gnd gnd nmos L=0.18u W=0.6u

m313 r44 a5bar gnd gnd nmos L=0.18u W=0.6u

m314 r44 a4 gnd gnd nmos L=0.18u W=0.6u

m315 r44 a3 gnd gnd nmos L=0.18u W=0.6u

m316 r45 a9 gnd gnd nmos L=0.18u W=0.6u

m317 r45 a8bar gnd gnd nmos L=0.18u W=0.6u

m318 r45 a7 gnd gnd nmos L=0.18u W=0.6u

m319 r45 a6bar gnd gnd nmos L=0.18u W=0.6u

m320 r45 a5bar gnd gnd nmos L=0.18u W=0.6u

m321 r45 a4 gnd gnd nmos L=0.18u W=0.6u

m322 r45 a3bar gnd gnd nmos L=0.18u W=0.6u

m323 r46 a9 gnd gnd nmos L=0.18u W=0.6u

m324 r46 a8bar gnd gnd nmos L=0.18u W=0.6u

m325 r46 a7 gnd gnd nmos L=0.18u W=0.6u

m326 r46 a6bar gnd gnd nmos L=0.18u W=0.6u

m327 r46 a5bar gnd gnd nmos L=0.18u W=0.6u

m328 r46 a4bar gnd gnd nmos L=0.18u W=0.6u

m329 r46 a3 gnd gnd nmos L=0.18u W=0.6u

m330 r47 a9 gnd gnd nmos L=0.18u W=0.6u

m331 r47 a8bar gnd gnd nmos L=0.18u W=0.6u

m332 r47 a7 gnd gnd nmos L=0.18u W=0.6u

m333 r47 a6bar gnd gnd nmos L=0.18u W=0.6u

m334 r47 a5bar gnd gnd nmos L=0.18u W=0.6u

m335 r47 a4bar gnd gnd nmos L=0.18u W=0.6u

m336 r47 a3bar gnd gnd nmos L=0.18u W=0.6u

m337 r48 a9 gnd gnd nmos L=0.18u W=0.6u

m338 r48 a8bar gnd gnd nmos L=0.18u W=0.6u

m339 r48 a7bar gnd gnd nmos L=0.18u W=0.6u

m340 r48 a6 gnd gnd nmos L=0.18u W=0.6u

m341 r48 a5 gnd gnd nmos L=0.18u W=0.6u

m342 r48 a4 gnd gnd nmos L=0.18u W=0.6u

m343 r48 a3 gnd gnd nmos L=0.18u W=0.6u

m344 r49 a9 gnd gnd nmos L=0.18u W=0.6u

m345 r49 a8bar gnd gnd nmos L=0.18u W=0.6u

m346 r49 a7bar gnd gnd nmos L=0.18u W=0.6u

m347 r49 a6 gnd gnd nmos L=0.18u W=0.6u

m348 r49 a5 gnd gnd nmos L=0.18u W=0.6u

m349 r49 a4 gnd gnd nmos L=0.18u W=0.6u

m350 r49 a3bar gnd gnd nmos L=0.18u W=0.6u

m351 r50 a9 gnd gnd nmos L=0.18u W=0.6u

m352 r50 a8bar gnd gnd nmos L=0.18u W=0.6u

m353 r50 a7bar gnd gnd nmos L=0.18u W=0.6u

m354 r50 a6 gnd gnd nmos L=0.18u W=0.6u

m355 r50 a5 gnd gnd nmos L=0.18u W=0.6u

m356 r50 a4bar gnd gnd nmos L=0.18u W=0.6u

m357 r50 a3 gnd gnd nmos L=0.18u W=0.6u

m358 r51 a9 gnd gnd nmos L=0.18u W=0.6u

m359 r51 a8bar gnd gnd nmos L=0.18u W=0.6u

m360 r51 a7bar gnd gnd nmos L=0.18u W=0.6u

m361 r51 a6 gnd gnd nmos L=0.18u W=0.6u

m362 r51 a5 gnd gnd nmos L=0.18u W=0.6u

m363 r51 a4bar gnd gnd nmos L=0.18u W=0.6u

m364 r51 a3bar gnd gnd nmos L=0.18u W=0.6u

m365 r52 a9 gnd gnd nmos L=0.18u W=0.6u

m366 r52 a8bar gnd gnd nmos L=0.18u W=0.6u

m367 r52 a7bar gnd gnd nmos L=0.18u W=0.6u

m368 r52 a6 gnd gnd nmos L=0.18u W=0.6u

m369 r52 a5bar gnd gnd nmos L=0.18u W=0.6u

m370 r52 a4 gnd gnd nmos L=0.18u W=0.6u

m371 r52 a3 gnd gnd nmos L=0.18u W=0.6u

m372 r53 a9 gnd gnd nmos L=0.18u W=0.6u

m373 r53 a8bar gnd gnd nmos L=0.18u W=0.6u

m374 r53 a7bar gnd gnd nmos L=0.18u W=0.6u

m375 r53 a6 gnd gnd nmos L=0.18u W=0.6u

m376 r53 a5bar gnd gnd nmos L=0.18u W=0.6u

m377 r53 a4 gnd gnd nmos L=0.18u W=0.6u

m378 r53 a3bar gnd gnd nmos L=0.18u W=0.6u

m379 r54 a9 gnd gnd nmos L=0.18u W=0.6u

m380 r54 a8bar gnd gnd nmos L=0.18u W=0.6u

m381 r54 a7bar gnd gnd nmos L=0.18u W=0.6u

m382 r54 a6 gnd gnd nmos L=0.18u W=0.6u

m383 r54 a5bar gnd gnd nmos L=0.18u W=0.6u

m384 r54 a4bar gnd gnd nmos L=0.18u W=0.6u

m385 r54 a3 gnd gnd nmos L=0.18u W=0.6u

m386 r55 a9 gnd gnd nmos L=0.18u W=0.6u

m387 r55 a8bar gnd gnd nmos L=0.18u W=0.6u

m388 r55 a7bar gnd gnd nmos L=0.18u W=0.6u

m389 r55 a6 gnd gnd nmos L=0.18u W=0.6u

m390 r55 a5bar gnd gnd nmos L=0.18u W=0.6u

m391 r55 a4bar gnd gnd nmos L=0.18u W=0.6u

m392 r55 a3bar gnd gnd nmos L=0.18u W=0.6u

m393 r56 a9 gnd gnd nmos L=0.18u W=0.6u

m394 r56 a8bar gnd gnd nmos L=0.18u W=0.6u

m395 r56 a7bar gnd gnd nmos L=0.18u W=0.6u

m396 r56 a6bar gnd gnd nmos L=0.18u W=0.6u

m397 r56 a5 gnd gnd nmos L=0.18u W=0.6u

m398 r56 a4 gnd gnd nmos L=0.18u W=0.6u

m399 r56 a3 gnd gnd nmos L=0.18u W=0.6u

m400 r57 a9 gnd gnd nmos L=0.18u W=0.6u

m401 r57 a8bar gnd gnd nmos L=0.18u W=0.6u

m402 r57 a7bar gnd gnd nmos L=0.18u W=0.6u

m403 r57 a6bar gnd gnd nmos L=0.18u W=0.6u

m404 r57 a5 gnd gnd nmos L=0.18u W=0.6u

m405 r57 a4 gnd gnd nmos L=0.18u W=0.6u

m406 r57 a3bar gnd gnd nmos L=0.18u W=0.6u

m407 r58 a9 gnd gnd nmos L=0.18u W=0.6u

m408 r58 a8bar gnd gnd nmos L=0.18u W=0.6u

m409 r58 a7bar gnd gnd nmos L=0.18u W=0.6u

m410 r58 a6bar gnd gnd nmos L=0.18u W=0.6u

m411 r58 a5 gnd gnd nmos L=0.18u W=0.6u

m412 r58 a4bar gnd gnd nmos L=0.18u W=0.6u

m413 r58 a3 gnd gnd nmos L=0.18u W=0.6u

m414 r59 a9 gnd gnd nmos L=0.18u W=0.6u

m415 r59 a8bar gnd gnd nmos L=0.18u W=0.6u

m416 r59 a7bar gnd gnd nmos L=0.18u W=0.6u

m417 r59 a6bar gnd gnd nmos L=0.18u W=0.6u

m418 r59 a5 gnd gnd nmos L=0.18u W=0.6u

m419 r59 a4bar gnd gnd nmos L=0.18u W=0.6u

m420 r59 a3bar gnd gnd nmos L=0.18u W=0.6u

m421 r60 a9 gnd gnd nmos L=0.18u W=0.6u

m422 r60 a8bar gnd gnd nmos L=0.18u W=0.6u

m423 r60 a7bar gnd gnd nmos L=0.18u W=0.6u

m424 r60 a6bar gnd gnd nmos L=0.18u W=0.6u

m425 r60 a5bar gnd gnd nmos L=0.18u W=0.6u

m426 r60 a4 gnd gnd nmos L=0.18u W=0.6u

m427 r60 a3 gnd gnd nmos L=0.18u W=0.6u

m428 r61 a9 gnd gnd nmos L=0.18u W=0.6u

m429 r61 a8bar gnd gnd nmos L=0.18u W=0.6u

m430 r61 a7bar gnd gnd nmos L=0.18u W=0.6u

m431 r61 a6bar gnd gnd nmos L=0.18u W=0.6u

m432 r61 a5bar gnd gnd nmos L=0.18u W=0.6u

m433 r61 a4 gnd gnd nmos L=0.18u W=0.6u

m434 r61 a3bar gnd gnd nmos L=0.18u W=0.6u

m435 r62 a9 gnd gnd nmos L=0.18u W=0.6u

m436 r62 a8bar gnd gnd nmos L=0.18u W=0.6u

m437 r62 a7bar gnd gnd nmos L=0.18u W=0.6u

m438 r62 a6bar gnd gnd nmos L=0.18u W=0.6u

m439 r62 a5bar gnd gnd nmos L=0.18u W=0.6u

m440 r62 a4bar gnd gnd nmos L=0.18u W=0.6u

m441 r62 a3 gnd gnd nmos L=0.18u W=0.6u

m442 r63 a9 gnd gnd nmos L=0.18u W=0.6u

m443 r63 a8bar gnd gnd nmos L=0.18u W=0.6u

m444 r63 a7bar gnd gnd nmos L=0.18u W=0.6u

m445 r63 a6bar gnd gnd nmos L=0.18u W=0.6u

m446 r63 a5bar gnd gnd nmos L=0.18u W=0.6u

m447 r63 a4bar gnd gnd nmos L=0.18u W=0.6u

m448 r63 a3bar gnd gnd nmos L=0.18u W=0.6u

m449 r64 a9bar gnd gnd nmos L=0.18u W=0.6u

m450 r64 a8 gnd gnd nmos L=0.18u W=0.6u

m451 r64 a7 gnd gnd nmos L=0.18u W=0.6u

m452 r64 a6 gnd gnd nmos L=0.18u W=0.6u

m453 r64 a5 gnd gnd nmos L=0.18u W=0.6u

m454 r64 a4 gnd gnd nmos L=0.18u W=0.6u

m455 r64 a3 gnd gnd nmos L=0.18u W=0.6u

m456 r65 a9bar gnd gnd nmos L=0.18u W=0.6u

m457 r65 a8 gnd gnd nmos L=0.18u W=0.6u

m458 r65 a7 gnd gnd nmos L=0.18u W=0.6u

m459 r65 a6 gnd gnd nmos L=0.18u W=0.6u

m460 r65 a5 gnd gnd nmos L=0.18u W=0.6u

m461 r65 a4 gnd gnd nmos L=0.18u W=0.6u

m462 r65 a3bar gnd gnd nmos L=0.18u W=0.6u

m463 r66 a9bar gnd gnd nmos L=0.18u W=0.6u

m464 r66 a8 gnd gnd nmos L=0.18u W=0.6u

m465 r66 a7 gnd gnd nmos L=0.18u W=0.6u

m466 r66 a6 gnd gnd nmos L=0.18u W=0.6u

m467 r66 a5 gnd gnd nmos L=0.18u W=0.6u

m468 r66 a4bar gnd gnd nmos L=0.18u W=0.6u

m469 r66 a3 gnd gnd nmos L=0.18u W=0.6u

m470 r67 a9bar gnd gnd nmos L=0.18u W=0.6u

m471 r67 a8 gnd gnd nmos L=0.18u W=0.6u

m472 r67 a7 gnd gnd nmos L=0.18u W=0.6u

m473 r67 a6 gnd gnd nmos L=0.18u W=0.6u

m474 r67 a5 gnd gnd nmos L=0.18u W=0.6u

m475 r67 a4bar gnd gnd nmos L=0.18u W=0.6u

m476 r67 a3bar gnd gnd nmos L=0.18u W=0.6u

m477 r68 a9bar gnd gnd nmos L=0.18u W=0.6u

m478 r68 a8 gnd gnd nmos L=0.18u W=0.6u

m479 r68 a7 gnd gnd nmos L=0.18u W=0.6u

m480 r68 a6 gnd gnd nmos L=0.18u W=0.6u

m481 r68 a5bar gnd gnd nmos L=0.18u W=0.6u

m482 r68 a4 gnd gnd nmos L=0.18u W=0.6u

m483 r68 a3 gnd gnd nmos L=0.18u W=0.6u

m484 r69 a9bar gnd gnd nmos L=0.18u W=0.6u

m485 r69 a8 gnd gnd nmos L=0.18u W=0.6u

m486 r69 a7 gnd gnd nmos L=0.18u W=0.6u

m487 r69 a6 gnd gnd nmos L=0.18u W=0.6u

m488 r69 a5bar gnd gnd nmos L=0.18u W=0.6u

m489 r69 a4 gnd gnd nmos L=0.18u W=0.6u

m490 r69 a3bar gnd gnd nmos L=0.18u W=0.6u

m491 r70 a9bar gnd gnd nmos L=0.18u W=0.6u

m492 r70 a8 gnd gnd nmos L=0.18u W=0.6u

m493 r70 a7 gnd gnd nmos L=0.18u W=0.6u

m494 r70 a6 gnd gnd nmos L=0.18u W=0.6u

m495 r70 a5bar gnd gnd nmos L=0.18u W=0.6u

m496 r70 a4bar gnd gnd nmos L=0.18u W=0.6u

m497 r70 a3 gnd gnd nmos L=0.18u W=0.6u

m498 r71 a9bar gnd gnd nmos L=0.18u W=0.6u

m499 r71 a8 gnd gnd nmos L=0.18u W=0.6u

m500 r71 a7 gnd gnd nmos L=0.18u W=0.6u

m501 r71 a6 gnd gnd nmos L=0.18u W=0.6u

m502 r71 a5bar gnd gnd nmos L=0.18u W=0.6u

m503 r71 a4bar gnd gnd nmos L=0.18u W=0.6u

m504 r71 a3bar gnd gnd nmos L=0.18u W=0.6u

m505 r72 a9bar gnd gnd nmos L=0.18u W=0.6u

m506 r72 a8 gnd gnd nmos L=0.18u W=0.6u

m507 r72 a7 gnd gnd nmos L=0.18u W=0.6u

m508 r72 a6bar gnd gnd nmos L=0.18u W=0.6u

m509 r72 a5 gnd gnd nmos L=0.18u W=0.6u

m510 r72 a4 gnd gnd nmos L=0.18u W=0.6u

m511 r72 a3 gnd gnd nmos L=0.18u W=0.6u

m512 r73 a9bar gnd gnd nmos L=0.18u W=0.6u

m513 r73 a8 gnd gnd nmos L=0.18u W=0.6u

m514 r73 a7 gnd gnd nmos L=0.18u W=0.6u

m515 r73 a6bar gnd gnd nmos L=0.18u W=0.6u

m516 r73 a5 gnd gnd nmos L=0.18u W=0.6u

m517 r73 a4 gnd gnd nmos L=0.18u W=0.6u

m518 r73 a3bar gnd gnd nmos L=0.18u W=0.6u

m519 r74 a9bar gnd gnd nmos L=0.18u W=0.6u

m520 r74 a8 gnd gnd nmos L=0.18u W=0.6u

m521 r74 a7 gnd gnd nmos L=0.18u W=0.6u

m522 r74 a6bar gnd gnd nmos L=0.18u W=0.6u

m523 r74 a5 gnd gnd nmos L=0.18u W=0.6u

m524 r74 a4bar gnd gnd nmos L=0.18u W=0.6u

m525 r74 a3 gnd gnd nmos L=0.18u W=0.6u

m526 r75 a9bar gnd gnd nmos L=0.18u W=0.6u

m527 r75 a8 gnd gnd nmos L=0.18u W=0.6u

m528 r75 a7 gnd gnd nmos L=0.18u W=0.6u

m529 r75 a6bar gnd gnd nmos L=0.18u W=0.6u

m530 r75 a5 gnd gnd nmos L=0.18u W=0.6u

m531 r75 a4bar gnd gnd nmos L=0.18u W=0.6u

m532 r75 a3bar gnd gnd nmos L=0.18u W=0.6u

m533 r76 a9bar gnd gnd nmos L=0.18u W=0.6u

m534 r76 a8 gnd gnd nmos L=0.18u W=0.6u

m535 r76 a7 gnd gnd nmos L=0.18u W=0.6u

m536 r76 a6bar gnd gnd nmos L=0.18u W=0.6u

m537 r76 a5bar gnd gnd nmos L=0.18u W=0.6u

m538 r76 a4 gnd gnd nmos L=0.18u W=0.6u

m539 r76 a3 gnd gnd nmos L=0.18u W=0.6u

m540 r77 a9bar gnd gnd nmos L=0.18u W=0.6u

m541 r77 a8 gnd gnd nmos L=0.18u W=0.6u

m542 r77 a7 gnd gnd nmos L=0.18u W=0.6u

m543 r77 a6bar gnd gnd nmos L=0.18u W=0.6u

m544 r77 a5bar gnd gnd nmos L=0.18u W=0.6u

m545 r77 a4 gnd gnd nmos L=0.18u W=0.6u

m546 r77 a3bar gnd gnd nmos L=0.18u W=0.6u

m547 r78 a9bar gnd gnd nmos L=0.18u W=0.6u

m548 r78 a8 gnd gnd nmos L=0.18u W=0.6u

m549 r78 a7 gnd gnd nmos L=0.18u W=0.6u

m550 r78 a6bar gnd gnd nmos L=0.18u W=0.6u

m551 r78 a5bar gnd gnd nmos L=0.18u W=0.6u

m552 r78 a4bar gnd gnd nmos L=0.18u W=0.6u

m553 r78 a3 gnd gnd nmos L=0.18u W=0.6u

m554 r79 a9bar gnd gnd nmos L=0.18u W=0.6u

m555 r79 a8 gnd gnd nmos L=0.18u W=0.6u

m556 r79 a7 gnd gnd nmos L=0.18u W=0.6u

m557 r79 a6bar gnd gnd nmos L=0.18u W=0.6u

m558 r79 a5bar gnd gnd nmos L=0.18u W=0.6u

m559 r79 a4bar gnd gnd nmos L=0.18u W=0.6u

m560 r79 a3bar gnd gnd nmos L=0.18u W=0.6u

m561 r80 a9bar gnd gnd nmos L=0.18u W=0.6u

m562 r80 a8 gnd gnd nmos L=0.18u W=0.6u

m563 r80 a7bar gnd gnd nmos L=0.18u W=0.6u

m564 r80 a6 gnd gnd nmos L=0.18u W=0.6u

m565 r80 a5 gnd gnd nmos L=0.18u W=0.6u

m566 r80 a4 gnd gnd nmos L=0.18u W=0.6u

m567 r80 a3 gnd gnd nmos L=0.18u W=0.6u

m568 r81 a9bar gnd gnd nmos L=0.18u W=0.6u

m569 r81 a8 gnd gnd nmos L=0.18u W=0.6u

m570 r81 a7bar gnd gnd nmos L=0.18u W=0.6u

m571 r81 a6 gnd gnd nmos L=0.18u W=0.6u

m572 r81 a5 gnd gnd nmos L=0.18u W=0.6u

m573 r81 a4 gnd gnd nmos L=0.18u W=0.6u

m574 r81 a3bar gnd gnd nmos L=0.18u W=0.6u

m575 r82 a9bar gnd gnd nmos L=0.18u W=0.6u

m576 r82 a8 gnd gnd nmos L=0.18u W=0.6u

m577 r82 a7bar gnd gnd nmos L=0.18u W=0.6u

m578 r82 a6 gnd gnd nmos L=0.18u W=0.6u

m579 r82 a5 gnd gnd nmos L=0.18u W=0.6u

m580 r82 a4bar gnd gnd nmos L=0.18u W=0.6u

m581 r82 a3 gnd gnd nmos L=0.18u W=0.6u

m582 r83 a9bar gnd gnd nmos L=0.18u W=0.6u

m583 r83 a8 gnd gnd nmos L=0.18u W=0.6u

m584 r83 a7bar gnd gnd nmos L=0.18u W=0.6u

m585 r83 a6 gnd gnd nmos L=0.18u W=0.6u

m586 r83 a5 gnd gnd nmos L=0.18u W=0.6u

m587 r83 a4bar gnd gnd nmos L=0.18u W=0.6u

m588 r83 a3bar gnd gnd nmos L=0.18u W=0.6u

m589 r84 a9bar gnd gnd nmos L=0.18u W=0.6u

m590 r84 a8 gnd gnd nmos L=0.18u W=0.6u

m591 r84 a7bar gnd gnd nmos L=0.18u W=0.6u

m592 r84 a6 gnd gnd nmos L=0.18u W=0.6u

m593 r84 a5bar gnd gnd nmos L=0.18u W=0.6u

m594 r84 a4 gnd gnd nmos L=0.18u W=0.6u

m595 r84 a3 gnd gnd nmos L=0.18u W=0.6u

m596 r85 a9bar gnd gnd nmos L=0.18u W=0.6u

m597 r85 a8 gnd gnd nmos L=0.18u W=0.6u

m598 r85 a7bar gnd gnd nmos L=0.18u W=0.6u

m599 r85 a6 gnd gnd nmos L=0.18u W=0.6u

m600 r85 a5bar gnd gnd nmos L=0.18u W=0.6u

m601 r85 a4 gnd gnd nmos L=0.18u W=0.6u

m602 r85 a3bar gnd gnd nmos L=0.18u W=0.6u

m603 r86 a9bar gnd gnd nmos L=0.18u W=0.6u

m604 r86 a8 gnd gnd nmos L=0.18u W=0.6u

m605 r86 a7bar gnd gnd nmos L=0.18u W=0.6u

m606 r86 a6 gnd gnd nmos L=0.18u W=0.6u

m607 r86 a5bar gnd gnd nmos L=0.18u W=0.6u

m608 r86 a4bar gnd gnd nmos L=0.18u W=0.6u

m609 r86 a3 gnd gnd nmos L=0.18u W=0.6u

m610 r87 a9bar gnd gnd nmos L=0.18u W=0.6u

m611 r87 a8 gnd gnd nmos L=0.18u W=0.6u

m612 r87 a7bar gnd gnd nmos L=0.18u W=0.6u

m613 r87 a6 gnd gnd nmos L=0.18u W=0.6u

m614 r87 a5bar gnd gnd nmos L=0.18u W=0.6u

m615 r87 a4bar gnd gnd nmos L=0.18u W=0.6u

m616 r87 a3bar gnd gnd nmos L=0.18u W=0.6u

m617 r88 a9bar gnd gnd nmos L=0.18u W=0.6u

m618 r88 a8 gnd gnd nmos L=0.18u W=0.6u

m619 r88 a7bar gnd gnd nmos L=0.18u W=0.6u

m620 r88 a6bar gnd gnd nmos L=0.18u W=0.6u

m621 r88 a5 gnd gnd nmos L=0.18u W=0.6u

m622 r88 a4 gnd gnd nmos L=0.18u W=0.6u

m623 r88 a3 gnd gnd nmos L=0.18u W=0.6u

m624 r89 a9bar gnd gnd nmos L=0.18u W=0.6u

m625 r89 a8 gnd gnd nmos L=0.18u W=0.6u

m626 r89 a7bar gnd gnd nmos L=0.18u W=0.6u

m627 r89 a6bar gnd gnd nmos L=0.18u W=0.6u

m628 r89 a5 gnd gnd nmos L=0.18u W=0.6u

m629 r89 a4 gnd gnd nmos L=0.18u W=0.6u

m630 r89 a3bar gnd gnd nmos L=0.18u W=0.6u

m631 r90 a9bar gnd gnd nmos L=0.18u W=0.6u

m632 r90 a8 gnd gnd nmos L=0.18u W=0.6u

m633 r90 a7bar gnd gnd nmos L=0.18u W=0.6u

m634 r90 a6bar gnd gnd nmos L=0.18u W=0.6u

m635 r90 a5 gnd gnd nmos L=0.18u W=0.6u

m636 r90 a4bar gnd gnd nmos L=0.18u W=0.6u

m637 r90 a3 gnd gnd nmos L=0.18u W=0.6u

m638 r91 a9bar gnd gnd nmos L=0.18u W=0.6u

m639 r91 a8 gnd gnd nmos L=0.18u W=0.6u

m640 r91 a7bar gnd gnd nmos L=0.18u W=0.6u

m641 r91 a6bar gnd gnd nmos L=0.18u W=0.6u

m642 r91 a5 gnd gnd nmos L=0.18u W=0.6u

m643 r91 a4bar gnd gnd nmos L=0.18u W=0.6u

m644 r91 a3bar gnd gnd nmos L=0.18u W=0.6u

m645 r92 a9bar gnd gnd nmos L=0.18u W=0.6u

m646 r92 a8 gnd gnd nmos L=0.18u W=0.6u

m647 r92 a7bar gnd gnd nmos L=0.18u W=0.6u

m648 r92 a6bar gnd gnd nmos L=0.18u W=0.6u

m649 r92 a5bar gnd gnd nmos L=0.18u W=0.6u

m650 r92 a4 gnd gnd nmos L=0.18u W=0.6u

m651 r92 a3 gnd gnd nmos L=0.18u W=0.6u

m652 r93 a9bar gnd gnd nmos L=0.18u W=0.6u

m653 r93 a8 gnd gnd nmos L=0.18u W=0.6u

m654 r93 a7bar gnd gnd nmos L=0.18u W=0.6u

m655 r93 a6bar gnd gnd nmos L=0.18u W=0.6u

m656 r93 a5bar gnd gnd nmos L=0.18u W=0.6u

m657 r93 a4 gnd gnd nmos L=0.18u W=0.6u

m658 r93 a3bar gnd gnd nmos L=0.18u W=0.6u

m659 r94 a9bar gnd gnd nmos L=0.18u W=0.6u

m660 r94 a8 gnd gnd nmos L=0.18u W=0.6u

m661 r94 a7bar gnd gnd nmos L=0.18u W=0.6u

m662 r94 a6bar gnd gnd nmos L=0.18u W=0.6u

m663 r94 a5bar gnd gnd nmos L=0.18u W=0.6u

m664 r94 a4bar gnd gnd nmos L=0.18u W=0.6u

m665 r94 a3 gnd gnd nmos L=0.18u W=0.6u

m666 r95 a9bar gnd gnd nmos L=0.18u W=0.6u

m667 r95 a8 gnd gnd nmos L=0.18u W=0.6u

m668 r95 a7bar gnd gnd nmos L=0.18u W=0.6u

m669 r95 a6bar gnd gnd nmos L=0.18u W=0.6u

m670 r95 a5bar gnd gnd nmos L=0.18u W=0.6u

m671 r95 a4bar gnd gnd nmos L=0.18u W=0.6u

m672 r95 a3bar gnd gnd nmos L=0.18u W=0.6u

m673 r96 a9bar gnd gnd nmos L=0.18u W=0.6u

m674 r96 a8bar gnd gnd nmos L=0.18u W=0.6u

m675 r96 a7 gnd gnd nmos L=0.18u W=0.6u

m676 r96 a6 gnd gnd nmos L=0.18u W=0.6u

m677 r96 a5 gnd gnd nmos L=0.18u W=0.6u

m678 r96 a4 gnd gnd nmos L=0.18u W=0.6u

m679 r96 a3 gnd gnd nmos L=0.18u W=0.6u

m680 r97 a9bar gnd gnd nmos L=0.18u W=0.6u

m681 r97 a8bar gnd gnd nmos L=0.18u W=0.6u

m682 r97 a7 gnd gnd nmos L=0.18u W=0.6u

m683 r97 a6 gnd gnd nmos L=0.18u W=0.6u

m684 r97 a5 gnd gnd nmos L=0.18u W=0.6u

m685 r97 a4 gnd gnd nmos L=0.18u W=0.6u

m686 r97 a3bar gnd gnd nmos L=0.18u W=0.6u

m687 r98 a9bar gnd gnd nmos L=0.18u W=0.6u

m688 r98 a8bar gnd gnd nmos L=0.18u W=0.6u

m689 r98 a7 gnd gnd nmos L=0.18u W=0.6u

m690 r98 a6 gnd gnd nmos L=0.18u W=0.6u

m691 r98 a5 gnd gnd nmos L=0.18u W=0.6u

m692 r98 a4bar gnd gnd nmos L=0.18u W=0.6u

m693 r98 a3 gnd gnd nmos L=0.18u W=0.6u

m694 r99 a9bar gnd gnd nmos L=0.18u W=0.6u

m695 r99 a8bar gnd gnd nmos L=0.18u W=0.6u

m696 r99 a7 gnd gnd nmos L=0.18u W=0.6u

m697 r99 a6 gnd gnd nmos L=0.18u W=0.6u

m698 r99 a5 gnd gnd nmos L=0.18u W=0.6u

m699 r99 a4bar gnd gnd nmos L=0.18u W=0.6u

m700 r99 a3bar gnd gnd nmos L=0.18u W=0.6u

m701 r100 a9bar gnd gnd nmos L=0.18u W=0.6u

m702 r100 a8bar gnd gnd nmos L=0.18u W=0.6u

m703 r100 a7 gnd gnd nmos L=0.18u W=0.6u

m704 r100 a6 gnd gnd nmos L=0.18u W=0.6u

m705 r100 a5bar gnd gnd nmos L=0.18u W=0.6u

m706 r100 a4 gnd gnd nmos L=0.18u W=0.6u

m707 r100 a3 gnd gnd nmos L=0.18u W=0.6u

m708 r101 a9bar gnd gnd nmos L=0.18u W=0.6u

m709 r101 a8bar gnd gnd nmos L=0.18u W=0.6u

m710 r101 a7 gnd gnd nmos L=0.18u W=0.6u

m711 r101 a6 gnd gnd nmos L=0.18u W=0.6u

m712 r101 a5bar gnd gnd nmos L=0.18u W=0.6u

m713 r101 a4 gnd gnd nmos L=0.18u W=0.6u

m714 r101 a3bar gnd gnd nmos L=0.18u W=0.6u

m715 r102 a9bar gnd gnd nmos L=0.18u W=0.6u

m716 r102 a8bar gnd gnd nmos L=0.18u W=0.6u

m717 r102 a7 gnd gnd nmos L=0.18u W=0.6u

m718 r102 a6 gnd gnd nmos L=0.18u W=0.6u

m719 r102 a5bar gnd gnd nmos L=0.18u W=0.6u

m720 r102 a4bar gnd gnd nmos L=0.18u W=0.6u

m721 r102 a3 gnd gnd nmos L=0.18u W=0.6u

m722 r103 a9bar gnd gnd nmos L=0.18u W=0.6u

m723 r103 a8bar gnd gnd nmos L=0.18u W=0.6u

m724 r103 a7 gnd gnd nmos L=0.18u W=0.6u

m725 r103 a6 gnd gnd nmos L=0.18u W=0.6u

m726 r103 a5bar gnd gnd nmos L=0.18u W=0.6u

m727 r103 a4bar gnd gnd nmos L=0.18u W=0.6u

m728 r103 a3bar gnd gnd nmos L=0.18u W=0.6u

m729 r104 a9bar gnd gnd nmos L=0.18u W=0.6u

m730 r104 a8bar gnd gnd nmos L=0.18u W=0.6u

m731 r104 a7 gnd gnd nmos L=0.18u W=0.6u

m732 r104 a6bar gnd gnd nmos L=0.18u W=0.6u

m733 r104 a5 gnd gnd nmos L=0.18u W=0.6u

m734 r104 a4 gnd gnd nmos L=0.18u W=0.6u

m735 r104 a3 gnd gnd nmos L=0.18u W=0.6u

m736 r105 a9bar gnd gnd nmos L=0.18u W=0.6u

m737 r105 a8bar gnd gnd nmos L=0.18u W=0.6u

m738 r105 a7 gnd gnd nmos L=0.18u W=0.6u

m739 r105 a6bar gnd gnd nmos L=0.18u W=0.6u

m740 r105 a5 gnd gnd nmos L=0.18u W=0.6u

m741 r105 a4 gnd gnd nmos L=0.18u W=0.6u

m742 r105 a3bar gnd gnd nmos L=0.18u W=0.6u

m743 r106 a9bar gnd gnd nmos L=0.18u W=0.6u

m744 r106 a8bar gnd gnd nmos L=0.18u W=0.6u

m745 r106 a7 gnd gnd nmos L=0.18u W=0.6u

m746 r106 a6bar gnd gnd nmos L=0.18u W=0.6u

m747 r106 a5 gnd gnd nmos L=0.18u W=0.6u

m748 r106 a4bar gnd gnd nmos L=0.18u W=0.6u

m749 r106 a3 gnd gnd nmos L=0.18u W=0.6u

m750 r107 a9bar gnd gnd nmos L=0.18u W=0.6u

m751 r107 a8bar gnd gnd nmos L=0.18u W=0.6u

m752 r107 a7 gnd gnd nmos L=0.18u W=0.6u

m753 r107 a6bar gnd gnd nmos L=0.18u W=0.6u

m754 r107 a5 gnd gnd nmos L=0.18u W=0.6u

m755 r107 a4bar gnd gnd nmos L=0.18u W=0.6u

m756 r107 a3bar gnd gnd nmos L=0.18u W=0.6u

m757 r108 a9bar gnd gnd nmos L=0.18u W=0.6u

m758 r108 a8bar gnd gnd nmos L=0.18u W=0.6u

m759 r108 a7 gnd gnd nmos L=0.18u W=0.6u

m760 r108 a6bar gnd gnd nmos L=0.18u W=0.6u

m761 1108 a5bar gnd gnd nmos L=0.18u W=0.6u

m762 r108 a4 gnd gnd nmos L=0.18u W=0.6u

m763 r108 a3 gnd gnd nmos L=0.18u W=0.6u

m764 r109 a9bar gnd gnd nmos L=0.18u W=0.6u

m765 r109 a8bar gnd gnd nmos L=0.18u W=0.6u

m766 r109 a7 gnd gnd nmos L=0.18u W=0.6u

m767 r109 a6bar gnd gnd nmos L=0.18u W=0.6u

m768 r109 a5bar gnd gnd nmos L=0.18u W=0.6u

m769 r109 a4 gnd gnd nmos L=0.18u W=0.6u

m770 r109 a3bar gnd gnd nmos L=0.18u W=0.6u

m771 r110 a9bar gnd gnd nmos L=0.18u W=0.6u

m772 r110 a8bar gnd gnd nmos L=0.18u W=0.6u

m773 r110 a7 gnd gnd nmos L=0.18u W=0.6u

m774 r110 a6bar gnd gnd nmos L=0.18u W=0.6u

m775 r110 a5bar gnd gnd nmos L=0.18u W=0.6u

m776 r110 a4bar gnd gnd nmos L=0.18u W=0.6u

m777 r110 a3 gnd gnd nmos L=0.18u W=0.6u

m778 r111 a9bar gnd gnd nmos L=0.18u W=0.6u

m779 r111 a8bar gnd gnd nmos L=0.18u W=0.6u

m780 r111 a7 gnd gnd nmos L=0.18u W=0.6u

m781 r111 a6bar gnd gnd nmos L=0.18u W=0.6u

m782 r111 a5bar gnd gnd nmos L=0.18u W=0.6u

m783 r111 a4bar gnd gnd nmos L=0.18u W=0.6u

m784 r111 a3bar gnd gnd nmos L=0.18u W=0.6u

m785 r112 a9bar gnd gnd nmos L=0.18u W=0.6u

m786 r112 a8bar gnd gnd nmos L=0.18u W=0.6u

m787 r112 a7bar gnd gnd nmos L=0.18u W=0.6u

m788 r112 a6 gnd gnd nmos L=0.18u W=0.6u

m789 r112 a5 gnd gnd nmos L=0.18u W=0.6u

m790 r112 a4 gnd gnd nmos L=0.18u W=0.6u

m791 r112 a3 gnd gnd nmos L=0.18u W=0.6u

m792 r113 a9bar gnd gnd nmos L=0.18u W=0.6u

m793 r113 a8bar gnd gnd nmos L=0.18u W=0.6u

m794 r113 a7bar gnd gnd nmos L=0.18u W=0.6u

m795 r113 a6 gnd gnd nmos L=0.18u W=0.6u

m796 r113 a5 gnd gnd nmos L=0.18u W=0.6u

m797 r113 a4 gnd gnd nmos L=0.18u W=0.6u

m798 r113 a3bar gnd gnd nmos L=0.18u W=0.6u

m799 r114 a9bar gnd gnd nmos L=0.18u W=0.6u

m800 r114 a8bar gnd gnd nmos L=0.18u W=0.6u

m801 r114 a7bar gnd gnd nmos L=0.18u W=0.6u

m802 r114 a6 gnd gnd nmos L=0.18u W=0.6u

m803 r114 a5 gnd gnd nmos L=0.18u W=0.6u

m804 r114 a4bar gnd gnd nmos L=0.18u W=0.6u

m805 r114 a3 gnd gnd nmos L=0.18u W=0.6u

m806 r115 a9bar gnd gnd nmos L=0.18u W=0.6u

m807 r115 a8bar gnd gnd nmos L=0.18u W=0.6u

m808 r115 a7bar gnd gnd nmos L=0.18u W=0.6u

m809 r115 a6 gnd gnd nmos L=0.18u W=0.6u

m810 r115 a5 gnd gnd nmos L=0.18u W=0.6u

m811 r115 a4bar gnd gnd nmos L=0.18u W=0.6u

m812 r115 a3bar gnd gnd nmos L=0.18u W=0.6u

m813 r116 a9bar gnd gnd nmos L=0.18u W=0.6u

m814 r116 a8bar gnd gnd nmos L=0.18u W=0.6u

m815 r116 a7bar gnd gnd nmos L=0.18u W=0.6u

m816 r116 a6 gnd gnd nmos L=0.18u W=0.6u

m817 r116 a5bar gnd gnd nmos L=0.18u W=0.6u

m818 r116 a4 gnd gnd nmos L=0.18u W=0.6u

m819 r116 a3 gnd gnd nmos L=0.18u W=0.6u

m820 r117 a9bar gnd gnd nmos L=0.18u W=0.6u

m821 r117 a8bar gnd gnd nmos L=0.18u W=0.6u

m822 r117 a7bar gnd gnd nmos L=0.18u W=0.6u

m823 r117 a6 gnd gnd nmos L=0.18u W=0.6u

m824 r117 a5bar gnd gnd nmos L=0.18u W=0.6u

m825 r117 a4 gnd gnd nmos L=0.18u W=0.6u

m826 r117 a3bar gnd gnd nmos L=0.18u W=0.6u

m827 r118 a9bar gnd gnd nmos L=0.18u W=0.6u

m828 r118 a8bar gnd gnd nmos L=0.18u W=0.6u

m829 r118 a7bar gnd gnd nmos L=0.18u W=0.6u

m830 r118 a6 gnd gnd nmos L=0.18u W=0.6u

m831 r118 a5bar gnd gnd nmos L=0.18u W=0.6u

m832 r118 a4bar gnd gnd nmos L=0.18u W=0.6u

m833 r118 a3 gnd gnd nmos L=0.18u W=0.6u

m834 r119 a9bar gnd gnd nmos L=0.18u W=0.6u

m835 r119 a8bar gnd gnd nmos L=0.18u W=0.6u

m836 r119 a7bar gnd gnd nmos L=0.18u W=0.6u

m837 r119 a6 gnd gnd nmos L=0.18u W=0.6u

m838 r119 a5bar gnd gnd nmos L=0.18u W=0.6u

m839 r119 a4bar gnd gnd nmos L=0.18u W=0.6u

m840 r119 a3bar gnd gnd nmos L=0.18u W=0.6u

m841 r120 a9bar gnd gnd nmos L=0.18u W=0.6u

m842 r120 a8bar gnd gnd nmos L=0.18u W=0.6u

m843 r120 a7bar gnd gnd nmos L=0.18u W=0.6u

m844 r120 a6bar gnd gnd nmos L=0.18u W=0.6u

m845 r120 a5 gnd gnd nmos L=0.18u W=0.6u

m846 r120 a4 gnd gnd nmos L=0.18u W=0.6u

m847 r120 a3 gnd gnd nmos L=0.18u W=0.6u

m848 r121 a9bar gnd gnd nmos L=0.18u W=0.6u

m849 r121 a8bar gnd gnd nmos L=0.18u W=0.6u

m850 r121 a7bar gnd gnd nmos L=0.18u W=0.6u

m851 r121 a6bar gnd gnd nmos L=0.18u W=0.6u

m852 r121 a5 gnd gnd nmos L=0.18u W=0.6u

m853 r121 a4 gnd gnd nmos L=0.18u W=0.6u

m854 r121 a3bar gnd gnd nmos L=0.18u W=0.6u

m855 r122 a9bar gnd gnd nmos L=0.18u W=0.6u

m856 r122 a8bar gnd gnd nmos L=0.18u W=0.6u

m857 r122 a7bar gnd gnd nmos L=0.18u W=0.6u

m858 r122 a6bar gnd gnd nmos L=0.18u W=0.6u

m859 r122 a5 gnd gnd nmos L=0.18u W=0.6u

m860 r122 a4bar gnd gnd nmos L=0.18u W=0.6u

m861 r122 a3 gnd gnd nmos L=0.18u W=0.6u

m862 r123 a9bar gnd gnd nmos L=0.18u W=0.6u

m863 r123 a8bar gnd gnd nmos L=0.18u W=0.6u

m864 r123 a7bar gnd gnd nmos L=0.18u W=0.6u

m865 r123 a6bar gnd gnd nmos L=0.18u W=0.6u

m866 r123 a5 gnd gnd nmos L=0.18u W=0.6u

m867 r123 a4bar gnd gnd nmos L=0.18u W=0.6u

m868 r123 a3bar gnd gnd nmos L=0.18u W=0.6u

m869 r124 a9bar gnd gnd nmos L=0.18u W=0.6u

m870 r124 a8bar gnd gnd nmos L=0.18u W=0.6u

m871 r124 a7bar gnd gnd nmos L=0.18u W=0.6u

m872 r124 a6bar gnd gnd nmos L=0.18u W=0.6u

m873 r124 a5bar gnd gnd nmos L=0.18u W=0.6u

m874 r124 a4 gnd gnd nmos L=0.18u W=0.6u

m875 r124 a3 gnd gnd nmos L=0.18u W=0.6u

m876 r125 a9bar gnd gnd nmos L=0.18u W=0.6u

m877 r125 a8bar gnd gnd nmos L=0.18u W=0.6u

m878 r125 a7bar gnd gnd nmos L=0.18u W=0.6u

m879 r125 a6bar gnd gnd nmos L=0.18u W=0.6u

m880 r125 a5bar gnd gnd nmos L=0.18u W=0.6u

m881 r125 a4 gnd gnd nmos L=0.18u W=0.6u

m882 r125 a3bar gnd gnd nmos L=0.18u W=0.6u

m883 r126 a9bar gnd gnd nmos L=0.18u W=0.6u

m884 r126 a8bar gnd gnd nmos L=0.18u W=0.6u

m885 r126 a7bar gnd gnd nmos L=0.18u W=0.6u

m886 r126 a6bar gnd gnd nmos L=0.18u W=0.6u

m887 r126 a5bar gnd gnd nmos L=0.18u W=0.6u

m888 r126 a4bar gnd gnd nmos L=0.18u W=0.6u

m889 r126 a3 gnd gnd nmos L=0.18u W=0.6u

m890 r127 a9bar gnd gnd nmos L=0.18u W=0.6u

m891 r127 a8bar gnd gnd nmos L=0.18u W=0.6u

m892 r127 a7bar gnd gnd nmos L=0.18u W=0.6u

m893 r127 a6bar gnd gnd nmos L=0.18u W=0.6u

m894 r127 a5bar gnd gnd nmos L=0.18u W=0.6u

m895 r127 a4bar gnd gnd nmos L=0.18u W=0.6u

m896 r127 a3bar gnd gnd nmos L=0.18u W=0.6u

*=====================================

*======================================

m897 r0 DEbar vdd vdd pmos L=0.18u W=1.2u

m898 r1 DEbar vdd vdd pmos L=0.18u W=1.2u

m899 r2 DEbar vdd vdd pmos L=0.18u W=1.2u

m900 r3 DEbar vdd vdd pmos L=0.18u W=1.2u

m901 r4 DEbar vdd vdd pmos L=0.18u W=1.2u

m902 r5 DEbar vdd vdd pmos L=0.18u W=1.2u

m903 r6 DEbar vdd vdd pmos L=0.18u W=1.2u

m904 r7 DEbar vdd vdd pmos L=0.18u W=1.2u

m905 r8 DEbar vdd vdd pmos L=0.18u W=1.2u

m906 r9 DEbar vdd vdd pmos L=0.18u W=1.2u

m907 r10 DEbar vdd vdd pmos L=0.18u W=1.2u

m908 r11 DEbar vdd vdd pmos L=0.18u W=1.2u

m909 r12 DEbar vdd vdd pmos L=0.18u W=1.2u

m910 r13 DEbar vdd vdd pmos L=0.18u W=1.2u

m911 r14 DEbar vdd vdd pmos L=0.18u W=1.2u

m912 r15 DEbar vdd vdd pmos L=0.18u W=1.2u

m913 r16 DEbar vdd vdd pmos L=0.18u W=1.2u

m914 r17 DEbar vdd vdd pmos L=0.18u W=1.2u

m915 r18 DEbar vdd vdd pmos L=0.18u W=1.2u

m916 r19 DEbar vdd vdd pmos L=0.18u W=1.2u

m917 r20 DEbar vdd vdd pmos L=0.18u W=1.2u

m918 r21 DEbar vdd vdd pmos L=0.18u W=1.2u

m919 r22 DEbar vdd vdd pmos L=0.18u W=1.2u

m920 r23 DEbar vdd vdd pmos L=0.18u W=1.2u

m921 r24 DEbar vdd vdd pmos L=0.18u W=1.2u

m922 r25 DEbar vdd vdd pmos L=0.18u W=1.2u

m923 r26 DEbar vdd vdd pmos L=0.18u W=1.2u

m924 r27 DEbar vdd vdd pmos L=0.18u W=1.2u

m925 r28 DEbar vdd vdd pmos L=0.18u W=1.2u

m926 r29 DEbar vdd vdd pmos L=0.18u W=1.2u

m927 r30 DEbar vdd vdd pmos L=0.18u W=1.2u

m928 r31 DEbar vdd vdd pmos L=0.18u W=1.2u

m929 r32 DEbar vdd vdd pmos L=0.18u W=1.2u

m930 r33 DEbar vdd vdd pmos L=0.18u W=1.2u

m931 r34 DEbar vdd vdd pmos L=0.18u W=1.2u

m932 r35 DEbar vdd vdd pmos L=0.18u W=1.2u

m933 r36 DEbar vdd vdd pmos L=0.18u W=1.2u

m934 r37 DEbar vdd vdd pmos L=0.18u W=1.2u

m935 r38 DEbar vdd vdd pmos L=0.18u W=1.2u

m936 r39 DEbar vdd vdd pmos L=0.18u W=1.2u

m937 r40 DEbar vdd vdd pmos L=0.18u W=1.2u

m938 r41 DEbar vdd vdd pmos L=0.18u W=1.2u

m939 r42 DEbar vdd vdd pmos L=0.18u W=1.2u

m940 r43 DEbar vdd vdd pmos L=0.18u W=1.2u

m941 r44 DEbar vdd vdd pmos L=0.18u W=1.2u

m942 r45 DEbar vdd vdd pmos L=0.18u W=1.2u

m943 r46 DEbar vdd vdd pmos L=0.18u W=1.2u

m944 r47 DEbar vdd vdd pmos L=0.18u W=1.2u

m945 r48 DEbar vdd vdd pmos L=0.18u W=1.2u

m946 r49 DEbar vdd vdd pmos L=0.18u W=1.2u

m947 r50 DEbar vdd vdd pmos L=0.18u W=1.2u

m948 r51 DEbar vdd vdd pmos L=0.18u W=1.2u

m949 r52 DEbar vdd vdd pmos L=0.18u W=1.2u

m950 r53 DEbar vdd vdd pmos L=0.18u W=1.2u

m951 r54 DEbar vdd vdd pmos L=0.18u W=1.2u

m952 r55 DEbar vdd vdd pmos L=0.18u W=1.2u

m953 r56 DEbar vdd vdd pmos L=0.18u W=1.2u

m954 r57 DEbar vdd vdd pmos L=0.18u W=1.2u

m955 r58 DEbar vdd vdd pmos L=0.18u W=1.2u

m956 r59 DEbar vdd vdd pmos L=0.18u W=1.2u

m957 r60 DEbar vdd vdd pmos L=0.18u W=1.2u

m958 r61 DEbar vdd vdd pmos L=0.18u W=1.2u

m959 r62 DEbar vdd vdd pmos L=0.18u W=1.2u

m960 r63 DEbar vdd vdd pmos L=0.18u W=1.2u

m961 r64 DEbar vdd vdd pmos L=0.18u W=1.2u

m962 r65 DEbar vdd vdd pmos L=0.18u W=1.2u

m963 r66 DEbar vdd vdd pmos L=0.18u W=1.2u

m964 r67 DEbar vdd vdd pmos L=0.18u W=1.2u

m965 r68 DEbar vdd vdd pmos L=0.18u W=1.2u

m966 r69 DEbar vdd vdd pmos L=0.18u W=1.2u

m967 r70 DEbar vdd vdd pmos L=0.18u W=1.2u

m968 r71 DEbar vdd vdd pmos L=0.18u W=1.2u

m969 r72 DEbar vdd vdd pmos L=0.18u W=1.2u

m970 r73 DEbar vdd vdd pmos L=0.18u W=1.2u

m971 r74 DEbar vdd vdd pmos L=0.18u W=1.2u

m972 r75 DEbar vdd vdd pmos L=0.18u W=1.2u

m973 r76 DEbar vdd vdd pmos L=0.18u W=1.2u

m974 r77 DEbar vdd vdd pmos L=0.18u W=1.2u

m975 r78 DEbar vdd vdd pmos L=0.18u W=1.2u

m976 r79 DEbar vdd vdd pmos L=0.18u W=1.2u

m977 r80 DEbar vdd vdd pmos L=0.18u W=1.2u

m978 r81 DEbar vdd vdd pmos L=0.18u W=1.2u

m979 r82 DEbar vdd vdd pmos L=0.18u W=1.2u

m980 r83 DEbar vdd vdd pmos L=0.18u W=1.2u

m981 r84 DEbar vdd vdd pmos L=0.18u W=1.2u

m982 r85 DEbar vdd vdd pmos L=0.18u W=1.2u

m983 r86 DEbar vdd vdd pmos L=0.18u W=1.2u

m984 r87 DEbar vdd vdd pmos L=0.18u W=1.2u

m985 r88 DEbar vdd vdd pmos L=0.18u W=1.2u

m986 r89 DEbar vdd vdd pmos L=0.18u W=1.2u

m987 r90 DEbar vdd vdd pmos L=0.18u W=1.2u

m988 r91 DEbar vdd vdd pmos L=0.18u W=1.2u

m989 r92 DEbar vdd vdd pmos L=0.18u W=1.2u

m990 r93 DEbar vdd vdd pmos L=0.18u W=1.2u

m991 r94 DEbar vdd vdd pmos L=0.18u W=1.2u

m992 r95 DEbar vdd vdd pmos L=0.18u W=1.2u

m993 r96 DEbar vdd vdd pmos L=0.18u W=1.2u

m994 r97 DEbar vdd vdd pmos L=0.18u W=1.2u

m995 r98 DEbar vdd vdd pmos L=0.18u W=1.2u

m996 r99 DEbar vdd vdd pmos L=0.18u W=1.2u

m997 r100 DEbar vdd vdd pmos L=0.18u W=1.2u

m998 r101 DEbar vdd vdd pmos L=0.18u W=1.2u

m999 r102 DEbar vdd vdd pmos L=0.18u W=1.2u

m1000 r103 DEbar vdd vdd pmos L=0.18u W=1.2u

m1001 r104 DEbar vdd vdd pmos L=0.18u W=1.2u

m1002 r105 DEbar vdd vdd pmos L=0.18u W=1.2u

m1003 r106 DEbar vdd vdd pmos L=0.18u W=1.2u

m1004 r107 DEbar vdd vdd pmos L=0.18u W=1.2u

m1005 r108 DEbar vdd vdd pmos L=0.18u W=1.2u

m1006 r109 DEbar vdd vdd pmos L=0.18u W=1.2u

m1007 r110 DEbar vdd vdd pmos L=0.18u W=1.2u

m1008 r111 DEbar vdd vdd pmos L=0.18u W=1.2u

m1009 r112 DEbar vdd vdd pmos L=0.18u W=1.2u

m1010 r113 DEbar vdd vdd pmos L=0.18u W=1.2u

m1011 r114 DEbar vdd vdd pmos L=0.18u W=1.2u

m1012 r115 DEbar vdd vdd pmos L=0.18u W=1.2u

m1013 r116 DEbar vdd vdd pmos L=0.18u W=1.2u

m1014 r117 DEbar vdd vdd pmos L=0.18u W=1.2u

m1015 r118 DEbar vdd vdd pmos L=0.18u W=1.2u

m1016 r119 DEbar vdd vdd pmos L=0.18u W=1.2u

m1017 r120 DEbar vdd vdd pmos L=0.18u W=1.2u

m1018 r121 DEbar vdd vdd pmos L=0.18u W=1.2u

m1019 r122 DEbar vdd vdd pmos L=0.18u W=1.2u

m1020 r123 DEbar vdd vdd pmos L=0.18u W=1.2u

m1021 r124 DEbar vdd vdd pmos L=0.18u W=1.2u

m1022 r125 DEbar vdd vdd pmos L=0.18u W=1.2u

m1023 r126 DEbar vdd vdd pmos L=0.18u W=1.2u

m1024 r127 DEbar vdd vdd pmos L=0.18u W=1.2u

*===================================

*====================================

*xnot0 a0 a0bar vdd inverter

*xnot1 a1 a1bar vdd inverter

*xnot2 a2 a2bar vdd inverter

*=====================================

m1025 a9bar a9 vdd vdd pmos L=0.18u W=1.2u

m1026 a9bar a9 gnd gnd nmos L=0.18u W=0.6u

m1027 a8bar a8 vdd vdd pmos L=0.18u W=1.2u

m1028 a8bar a8 gnd gnd nmos L=0.18u W=0.6u

m1029 a7bar a7 vdd vdd pmos L=0.18u W=1.2u

m1030 a7bar a7 gnd gnd nmos L=0.18u W=0.6u

m1031 a6bar a6 vdd vdd pmos L=0.18u W=1.2u

m1032 a6bar a6 gnd gnd nmos L=0.18u W=0.6u

m1033 a5bar a5 vdd vdd pmos L=0.18u W=1.2u

m1034 a5bar a5 gnd gnd nmos L=0.18u W=0.6u

m1035 a4bar a4 vdd vdd pmos L=0.18u W=1.2u

m1036 a4bar a4 gnd gnd nmos L=0.18u W=0.6u

m1037 a3bar a3 vdd vdd pmos L=0.18u W=1.2u

m1038 a3bar a3 gnd gnd nmos L=0.18u W=0.6u

*====================================

vvdd vdd gnd dc 1.8v

vDEbar DEbar gnd pulse(0 1.8 1n 1n 1n 3n 1300n)

va3 a3 gnd pulse(1.8 0 1n 1n 1n 5n 10n)

va4 a4 gnd pulse(1.8 0 1n 1n 1n 10n 20n)

va5 a5 gnd pulse(1.8 0 1n 1n 1n 20n 40n)

va6 a6 gnd pulse(1.8 0 1n 1n 1n 40n 80n)

va7 a7 gnd pulse(1.8 0 1n 1n 1n 80n 160n)

va8 a8 gnd pulse(1.8 0 1n 1n 1n 160n 320n)

va9 a9 gnd pulse(1.8 0 1n 1n 1n 320n 640n)

*=====================================

.tran 0 1400n

.plot tran v(a3) v(a3bar) v(a4) v(a4bar) v(a5) v(a5bar) v(a6) v(a6bar) v(a7) v(a7bar) v(a8) v(a8bar) v(a9) v(a9bar)

+ v(r0) v(r1) v(r2) v(r3) v(r4) v(r5) v(r6) v(r7) v(r8) v(r9)

+ v(r10) v(r11) v(r12) v(r13) v(r14) v(r15) v(r16) v(r17) v(r18) v(r19)

+ v(r20) v(r21) v(r22) v(r23) v(r24) v(r25) v(r26) v(r27) v(r28) v(r29)

+ v(r30) v(r31) v(r32) v(r33) v(r34) v(r35) v(r36) v(r37) v(r38) v(r39)

+ v(r40) v(r41) v(r42) v(r43) v(r44) v(r45) v(r46) v(r47) v(r48) v(r49)

+ v(r50) v(r51) v(r52) v(r53) v(r54) v(r55) v(r56) v(r57) v(r58) v(r59)

+ v(r60) v(r61) v(r62) v(r63) v(r64) v(r65) v(r66) v(r67) v(r68) v(r69)

+ v(r70) v(r71) v(r72) v(r73) v(r74) v(r75) v(r76) v(r77) v(r78) v(r79)

+ v(r80) v(r81) v(r82) v(r83) v(r84) v(r85) v(r86) v(r87) v(r88) v(r89)

+ v(r90) v(r91) v(r92) v(r93) v(r94) v(r95) v(r96) v(r97) v(r98) v(r99)

+ v(r100) v(r101) v(r102) v(r103) v(r104) v(r105) v(r106) v(r107) v(r108) v(r109)

+ v(r110) v(r111) v(r112) v(r113) v(r114) v(r115) v(r116) v(r117) v(r118) v(r119)

+ v(r120) v(r121) v(r122) v(r123) v(r124) v(r125) v(r126) v(r127)

.end

====================================================================

*sense amplifier

*=======================

.include "C:\Program Files\LTC\SwCADIII\lib\cmp\180nm_model.txt"

*=========================

m2 Y Ybar vdd vdd pmos L=0.18u W=1.2u

m1 Y Ybar n1 gnd nmos L=0.18u W=0.6u

m3 Ybar Y vdd vdd pmos L=0.18u W=1.2u

m4 Ybar Y n1 gnd nmos L=0.18u W=0.6u

m5 n1 SE gnd gnd nmos L=0.18u W=0.6u

vvdd vdd gnd dc 1.8v

vSE SE gnd pulse(1.8 0 1n 1n 1n 30n 60n)

vBL Y gnd pulse(1.8 0 1n 1n 1n 18n 36n)

*vBLbar BLbar gnd pulse(1.8v 0 1n 1n 1n 5n 10n)

.tran 0 100n

*.dc vvdd 0 1.8 0.025

.plot v(Y) v(Ybar)

.end

======================================================================